ЦИФРОВІ КОМПАРАТОРИ ЧАСТОТИ ТА ФАЗИ В СКЛАДІ СИСТЕМИ СТАБІЛІЗАЦІЇ ПОЛОЖЕННЯ РУХОМОЇ ПЛАТФОРМИ

Abstract

Urgency of the research. A dual-range, four-quadrant position stabilization system (PSS) of a brushless direct current motor (BLDC) as a part of movable platform (MP), in which the power stage is based on a quasi-resonant pulse converter (QRPC), has the better speed and accuracy characteristics in comparison with hard-switching PWM-based converters. Target setting. The BLDC PSS can be built on the basis of the classic multi-loop control system (MLCS), or on the pulse-frequency (PF-) domain. In PF-domain the task of speed control is transformed into the frequency comparing and matching task, and the position control is transformed into the phasecomparing and matching between the reference signal and the feedback signal. The development of specialized digital blocks of a frequency comparator (FK) and a phase comparator (PC) to perform the above tasks is a non-trivial task. Actual scientific researches and issues analysis. The earliest solutions of the FC, which should be correctly called the ‘frequency detector’ (FD), were implemented mixed-signal (contained both analog and digital nodes) due to their usage in a high-frequency phase-locked loop (PLL) system. A full-featured FC consists of two counters, comparator, a FD block, control finite-state machine (FSM), and a specialized combinational circuit. Uninvestigated parts of general matters defining. Existing FC blocks do not return a quantitative relation between measured frequencies, which can be used to predict dynamics, and are insensitive to the detection of small misalignments between frequencies, that, in turn, creates instability of determining the frequencies equality state. Existing PC blocks are unstable when the frequency of one of the measured signals reaches the system clock frequency, and also do not take into account the edges incoming order of the measured signals. The research objective. The article is devoted to the study and development of the structure of pure-digital FC and PC blocks, which will eliminate the disadvantages of existing solutions and are oriented for integration into PSS with QRPC in the power stage and MLCS operates in a PF-domain. The statement of basic materials. A novel technical solutions is proposed, developed and tested for pure-digital blocks of the FC and PC built on the basis of the field-programmable gate array (FPGA) by means of the hardware description language (VHDL). They allow not only to measure the sign of the inequality of frequency and phase between two periodic signals, but also to obtain the difference numerical values between them. Conclusions. The installation of the FC and PC blocks into the BLDC PSS leads to a significant reducing of FPGA hardware resources utilization and to the high reliability and noise immunity of the MLCS through the unruptured (continiously) nature of the signals. Both the proposed blocks are novel and have eliminated the inherent disadvantages of the existing blocks of the FC and PC due to the installation of additional digital nodes − synchronizers (pulse shorters and edge detectors), and also a hysteresis node that leads to increase the stability and solve the problem of detection near-to-equal frequencies and phases.