Field Programmable Gate Array Circuit Research Articles

Arterial Distension Monitoring Scheme Using FPGA-Based Inference Machine in Ultrasound Scanner Circuit System.

This paper presents an arterial distension monitoring scheme using a field-programmable gate array (FPGA)-based inference machine in an ultrasound scanner circuit system. An arterial distension monitoring requires a precise positioning of an ultrasound probe on an artery as a prerequisite. The proposed arterial distension monitoring scheme is based on a finite state machine that incorporates sequential support vector machines (SVMs) to assist in both coarse and fine adjustments of probe position. The SVMs sequentially perform recognitions of ultrasonic A-mode echo pattern for a human carotid artery. By employing sequential SVMs in combination with convolution and average pooling, the number of features for the inference machine is significantly reduced, resulting in less utilization of hardware resources in FPGA. The proposed arterial distension monitoring scheme was implemented in an FPGA (Artix7) with a resource utilization percentage less than 9.3%. To demonstrate the proposed scheme, we implemented a customized ultrasound scanner consisting of a single-element transducer, an FPGA, and analog interface circuits with discrete chips. In measurements, we set virtual coordinates on a human neck for 9 human subjects. The achieved accuracy of probe positioning inference is 88%, and the Pearson coefficient (r) of arterial distension estimation is 0.838.

Input/output corrective control of switched asynchronous sequential machines under arbitrary switching

This article presents a novel modeling and corrective control of switched asynchronous sequential machines (ASMs) with input/output submachines. In particular, the considered switched ASM is harnessed by the external switching signal that provokes arbitrary change of the mode or submachine. The existence of the external switching signal imposes unpredictable state drift opposite to model matching as well as ambiguity in determining the active submachine. We first present a state observer for state observation and identification of the active submachine. Based on the information delivered by the observer, we address the existence condition and design procedure for a corrective controller that matches the stable-state behavior of the closed-loop system to that of a reference model for every possible switching sequence. To demonstrate the validity and applicability of the proposed control scheme, we conduct hardware experiments on field-programmable gate array (FPGA) circuits for a space-borne digital system and provide convincing experimental results.

Hardware Sequence Combinators

Recent advances in formal methods for constructing parsers have employed the notion of combinators: primitive elemental parsers with well-defined methods for combining them in sequences or through choice. This paper explores the subtleties associated with leveraging sequence combinators to produce compact, custom hardware traffic validators. This involves a fully automated process that takes as input a formal grammar specifying message formats and produces a parsing circuit capable of validating traffic headers and payload content. The resulting circuit is deployed through network guard appliances that employ Field Programmable Gate Array (FPGA) devices, or alternatively, within the on-chip FPGA associated with System-on-Chip (SoC) devices, such as the Xilinx UltraScale MPSoC. Each guard appliance acts as a hidden “bump-in-the-wire” that either forwards or drops individual packets based on the message parsing outcome, thereby hardening network segments against zero-day attacks and persistent implants. Guards may operate on a wide variety traffic protocols and formats including TCP/IP, CAN/J1939, or MIL-STD-1553. The central step in parser construction is to build a collection of standard shift/reduce parsing tables that can be employed by a push-down automata to check each byte in a message. Typically, these tables are sparse, resulting in excessive use of FPGA circuit resources to represent them. By leveraging sequence combinators, along with other optimizations, we have been able to produce highly compact representations that can reduce table size by up to 95% for non-trivial grammars. Depending on the grammar, this translates directly into FPGA resource reductions. The reductions now make it viable to implement complex parsers on small, inexpensive FPGA’s, or alternatively combine parsers with encryption and encapsulation to enhance guard capabilities.

Design and Implementation of a Reconfigurable Corrective Control System Subject to Permanent Faults in the Controller.

This article presents a reconfiguration strategy for the corrective controller achieving model matching control of an input/state asynchronous sequential machine (ASM). The considered controller is vulnerable to permanent faults that degenerate a subset of the controller's states. If the controller has a certain amount of redundancy in terms of its states, one can build a reconfiguration scheme in which the functionality of degenerated states is taken over by supplementary states. The proposed reconfiguration scheme is superior to conventional methods of fault tolerance with hardware redundancy since the required number of redundant states is much smaller. Hardware experiments on field-programmable gate array (FPGA) circuits are provided to validate the applicability of the proposed scheme. The present study serves as the first research report on the reconfigurable corrective controller.

Design of an interface circuit system for mode-separation MEMS digital gyroscope

In this paper, a novel digital closed-loop interface circuit system of MEMS vibrating gyroscope is proposed, which includes driving, detection and quadrature circuits. Because of the high sensitivity and precision of the MEMS gyroscope, the interface circuit system is established under the condition of mode separation. The driving circuit of MEMS gyroscope adopts digital automatic gain control (AGC) to realize self-excitation closed-loop control, which makes the gyroscope system simple in structure and good in robustness. First, the working principle of the gyroscope’s sensitive structure is introduced and the system simulation model of the sensitive structure is developed. Second, a [Formula: see text] ADC and DAC with single-bit output are designed and the feasibility of the driving circuit design is verified by the system-level model. Third, the quadrature closed-loop correction circuit is designed to reduce the coupling of the quadrature component to the gyroscope detection circuit. The simulation results show that the quadrature correction loop can effectively reduce the influence of the quadrature coupling on the detection loop of MEMS gyroscope. Finally, the system-level model of the gyroscope is established by SIMULINK, the overall system performance of the gyroscope is analyzed, and the test system of MEMS gyroscope is built by field-programmable gate array (FPGA) and application specific integrated circuit (ASIC). The experiment verifies the feasibility of the digital interface circuit design, and the zero-bias instability of the gyroscope system is 1.0∘/h.

Fuzzy current analysis-based fault diagnostic of induction motor using hardware co-simulation with field programmable gate array

Introduction. Presently, signal analysis of stator current of induction motor has become a popular technique to assess the health state of asynchronous motor in order to avoid failures. The classical implementations of failure detection algorithms for rotating machines, based on microprogrammed sequential systems such as microprocessors and digital signal processing have shown their limitations in terms of speed and real time constraints, which requires the use of new technologies providing more efficient diagnostics such as application specific integrated circuit or field programmable gate array (FPGA). The purpose of this work is to study the contribution of the implementation of fuzzy logic on FPGA programmable logic circuits in the diagnosis of asynchronous machine failures for a phase unbalance and a missing phase faults cases. Methodology. In this work, we propose hardware architecture on FPGA of a failure detection algorithm for asynchronous machine based on fuzzy logic and motor current signal analysis by taking the RMS signal of stator current as a fault indicator signal. Results. The validation of the proposed architecture was carried out by a co-simulation hardware process between the ML402 boards equipped with a Virtex-4 FPGA circuit of the Xilinx type and Xilinx system generator under MATLAB/Simulink. Originality. The present work combined the performance of fuzzy logic techniques, the simplicity of stator current signal analysis algorithms and the execution power of ML402 FPGA board, for the fault diagnosis of induction machine achieving the best ratios speed/performance and simplicity/performance. Practical value. The emergence of this method has improved the performance of fault detection for asynchronous machine, especially in terms of hardware resource consumption, real-time online detection and speed of detection.

Dynamical analysis and synchronization control of flux-controlled memristive chaotic circuits and its FPGA-Based implementation

This paper focuses on addressing the synchronization control problem of memristive chaos through the investigation of a single feedback controller strategy. Our objective is to deploy this strategy on field-programmable gate arrays (FPGA) with the aim of bolstering the security and reliability of memristive chaotic synchronization control. Concurrently, we seek to enhance system performance and fulfill the diverse requirements of various applications. Initially, the study utilizes chaos synchronization theory and the Routh–Hurwitz stability criterion to devise a feedback controller with a single input. This controller plays a crucial role in establishing a synchronization system specifically designed for memristive chaos. Subsequently, the FPGA design approach utilizing DSP Builder is employed to create models for both the single-input feedback controller and the memristive chaotic synchronization control system. This approach facilitates the efficient translation of these theoretical concepts into practical digital circuit implementations. Finally, the paper concludes with an experimental analysis that verifies the feasibility and practical applicability of the FPGA circuit design for memristive chaotic synchronization control.

Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks

In this article, the modified Pietra-Ricci index detector (mPRIDe) is devised, and its field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs are reported. The mPRIDe attains lower implementation complexity with respect to its predecessor, without performance penalty. Moreover, the mPRIDe is blind, robust against time-varying noise and received signal powers, and exhibits the constant false alarm rate property. Two versions of the mPRIDe, namely mPRIDe v1 and mPRIDe v2, have been designed. The former privileges lower hardware complexity, whereas the latter aims lower latency, with both versions having a linear scalability with the number of sensors in cooperation. In comparison with the smallest area consumed by a state-of-the-art sensor, mPRIDe v1 and mPRIDe v2 consume 56.6% and 47.3% lower areas, respectively. The sensing times of the proposed sensors are 1.6 and 2.9 times better than the fastest sensing time of contemporary sensors. Moreover, the proposed designs deliver the lowest area-time-product and power-delay-product among state-of-the-art implementations. These metrics make both mPRIDe v1 and mPRIDe v2 the most hardware-efficient and power-efficient sensors reported in the literature.

A Heterogeneous Parallel Non-von Neumann Architecture System for Accurate and Efficient Machine Learning Molecular Dynamics

This paper proposes a special-purpose system to achieve high-accuracy and high-efficiency machine learning (ML) molecular dynamics (MD) calculations. The system consists of field programmable gate array (FPGA) and application specific integrated circuit (ASIC) working in heterogeneous parallelization. To be specific, a multiplication-less neural network (NN) is deployed on the non-von Neumann (NvN)-based ASIC (SilTerra 180 nm process) to evaluate atomic forces, which is the most computationally expensive part of MD. All other calculations of MD are done using FPGA (Xilinx XC7Z100). It is shown that, to achieve similar-level accuracy, the proposed NvN-based system based on low-end fabrication technologies (180 nm) is 1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> faster and 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> -10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{3}\times $</tex-math> </inline-formula> more energy efficiency than state-of-the-art vN-based MLMD using graphics processing units (GPUs) based on much more advanced technologies (12 nm), indicating superiority of the proposed NvN-based heterogeneous parallel architecture.

Self-Repairing Corrective Control for Input/Output Asynchronous Sequential Machines With Transient Faults

Fault-tolerant corrective control for input/output asynchronous sequential machines (ASMs) is studied in this article. In the present problem setting, not only the controlled ASM but also the corrective controller itself is vulnerable to transient faults. The fault outcome is aggravated when the transient fault occurs to the controller, since the adverse effect of the fault is propagated toward the controlled ASM. We first address a scheme of diagnosing transient faults by designing the state observer that induces the resultant faulty state based on the output burst. We then present the existence condition and design algorithm for a corrective controller that recovers the normal behavior of the closed-loop system against transient faults at the ASM, while achieving self-repair against those faults occurring to the controller. Hardware experiments on field-programmable gate array (FPGA) circuits are provided to validate the applicability of the proposed control methodology.

Field programmable gate array hardware in the loop validation of fuzzy direct torque control for induction machine drive

Introduction. Currently, the direct torque control is very popular in industry and is of great interest to scientists in the variable speed drive of asynchronous machines. This technique provides decoupling between torque control and flux without the need to use pulse width modulation or coordinate transformation. Nevertheless, this command presents two major importunities: the switching frequency is highly variable on the one hand, and on the other hand, the amplitude of the torque and stator flux ripples remain poorly controlled throughout the considered operating speed range. The novelty of this article proposes improvements in performance of direct torque control of asynchronous machines by development of a fuzzy direct torque control algorithm. This latter makes it possible to provide solutions to the major problems of this control technique, namely: torque ripples, flux ripples, and failure to control switching frequency. Purpose. The emergence of this method has given rise to various works whose objective is to show its performance, or to provide solutions to its limitations. Indeed, this work consists in validation of a fuzzy direct torque control architecture implemented on the ML402 development kit (based on the Xilinx Virtex-4 type field programmable gate array circuit), through hardware description language (VHDL) and Xilinx generator system. The obtained results showed the robustness of the control and sensorless in front of load and parameters variation of induction motor control. The research directions of the model were determined for the subsequent implementation of results with simulation samples.

DycSe: A Low-Power, Dynamic Reconfiguration Column Streaming-Based Convolution Engine for Resource-Aware Edge AI Accelerators

Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility.

Programming mechanism and characteristics of Sense-Switch pFlash cells

Sense-Switch pFlash is a common floating gate switching cell with the advantages of high integration, natural field-edge total dose radiation hardness, and high reliability. It is the core configuration cell of the field-programmable gate array (FPGA), and it can be used to realize radiation-hardened flash-based FPGA circuits. This study investigates the programming mechanism of the Sense-Switch pFlash device with dumbbell structure based on 0.13 μm eFlash technology and analyzes the influences of the device's programming and erasing methods on the threshold characteristics, on/off-state characteristics, and retention characteristics of Sense-Switch pFlash cells. It is found that there are multiple mechanisms in the programming process. Additionally, under certain programming and erasing voltage conditions, the threshold voltage and driving current of programming/erasing state depend on the pulse width, meaning that a fixed pulse width leads to specific threshold voltage and driving current values in the programming and erasing modes, which is called the pulse width modulation effect (PWME). Multi-level storage can be well obtained to expand the application of the Sense-Switch pFlash in the field of computing-in-memory and brain-inspired computing.

Development of digital image processing algorithms based on the Winograd method in general form and analysis of their computational complexity

The fast increase of the amount of quantitative and qualitative characteristics of digital visual data calls for the improvement of the performance of modern image processing devices. This article proposes new algorithms for 2D digital image processing based on the Winograd method in a general form. An analysis of the obtained results showed that the use of the Winograd method reduces the computational complexity of image processing by up to 84% compared to the traditional direct digital filtering method depending on the filter parameters and image fragments, while not affecting the quality of image processing. The resulting Winograd method transformation matrices and the algorithms developed can be used in image processing systems to improve the performance of the modern microelectronic devices that carry out image denoising, compression, and pattern recognition. Research directions that show promise for further research include hardware implementation on a field-programmable gate array and application-specific integrated circuit, development of algorithms for digital image processing based on the Winograd method in a general form for a 1D wavelet filter bank and for stride convolution used in convolutional neural networks.

Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits

High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).

A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers

Neural network pruning, which can be divided into unstructured pruning and structured pruning strategies, has been proven to be an efficient method to substantially reduce the number of computations of convolutional neural networks (CNNs). However, it remains difficult to combine the advantages of these two pruning strategies. This article proposes a high-performance accelerator for unstructured sparse CNNs. First, a convolution-based filter selection and clustering method (FSCM) is proposed to reorder unstructured sparse filters into uniform-size dense filters, eliminating redundant computations in the convolutional layers while maintaining a regular structure. In addition, a convolution and pooling calculation method (CPCM) is presented to reduce interlayers’ computational redundancy. Third, a hardware accelerator with high digital signal processing (DSP) efficiency is designed to take advantage of FSCM and CPCM. The proposed accelerator is implemented on a Xilinx XCVU9P platform at 300 MHz. With different CNN configurations, the performance and DSP efficiency for LeNet, AlexNet, and VGG16 are 1490.53 GOPS and 3.882, 913.85 GOPS and 1.785, and 862.16 GOPS and 1.68, respectively. Compared to previous field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs, the accelerator achieves up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15.43\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.73\times $ </tex-math></inline-formula> speedup in terms of performance and DSP efficiency.

Secure image encryption using high throughput architectures of PRINT cipher for radio frequency identification applications

With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.

Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA

Due to technological advancements and voltage scaling, leakage power has become an important concern in CMOS design. The implementation of a field-programmable gate array (FPGA) circuit utilizes a portion of the FPGA’s resources as compared to an application-specific integrated circuit (ASIC). Both the utilized and unutilized parts of the FPGA dissipate leakage power. In this work, two dynamic power gating techniques, PSG-1 and PSG-2, are proposed, which are able to reduce the leakage power of the 6-input look-up table (LUT) used in the Xilinx Spartan-6 series. The obtained results show that the proposed approaches PSG-1 and PSG-2 reduce average leakage power by 54.61% and 66.69%, respectively, at the expense of nominal area and delay overhead. The proposed method is also capable of lowering the average total power of the 6-input LUT. The suggested PSG-1 and PSG-2 approaches reduce average power by 53.75% and 60.83%, respectively. However, header-based power supply gating is extremely vulnerable to the negative-bias temperature instability (NBTI) aging effect and, due to this, the lifetime of the circuit is reduced considerably. Therefore, in this work, lifetime estimation-based analysis is performed by varying the stress probability of the sleep transistor. The results show that the LUT with PSG-1 and PSG-2 techniques has a lifetime of 4.55 years and 11.13 years, respectively. The stress time of the sleep transistor is 50% for the PSG-1 technique and 25% for the PSG-2 technique, respectively.

Robust input/output model matching of asynchronous sequential machines under intermittent actuator faults

A robust model matching control scheme for input/output asynchronous sequential machines (ASMs) with intermittent actuator faults is presented in the framework of corrective control. In our problem setting, certain actuator outputs are not transmitted to the machine temporarily owing to random faults. We first present a state observer that predicts the current stable state of the machine based on the output burst and control input, as well as diagnoses actuator faults. We then address the existence condition and design procedure for an output-feedback corrective controller that matches the input/output behavior of the closed-loop system to that of a reference model against intermittent loss of actuator outputs. To demonstrate the applicability of the proposed control method, we implement a practical asynchronous digital system with the developed corrective controller on the field-programmable gate array (FPGA) circuit. Experimental verifications using the FPGA circuit are also provided.

Real-time single-pixel imaging using a system on a chip field-programmable gate array

Unlike conventional imaging, the single-pixel imaging technique uses a single-element detector, which enables high sensitivity, broad wavelength, and noise robustness imaging. However, it has several challenges, particularly requiring extensive computations for image reconstruction with high image quality. Therefore, high-performance computers are required for real-time reconstruction with higher image quality. In this study, we developed a compact dedicated computer for single-pixel imaging using a system on a chip field-programmable gate array (FPGA), which enables real-time reconstruction at 40 frames per second with an image size of 128 × 128 pixels. An FPGA circuit was implemented with the proposed reconstruction algorithm to obtain higher image quality by introducing encoding mask pattern optimization. The dedicated computer can accelerate the reconstruction 10 times faster than a recent CPU. Because it is very compact compared with typical computers, it can expand the application of single-pixel imaging to the Internet of Things and outdoor applications.