Field Programmable Gate Array Board Research Articles

FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm.

Nowadays, generative adversarial network (GAN) is making continuous breakthroughs in many machine learning tasks. The popular GANs usually involve computation-intensive deconvolution operations, leading to limited real-time applications. Prior works have brought several accelerators for deconvolution, but all of them suffer from severe problems, such as computation imbalance and large memory requirements. In this article, we first introduce a novel fast transformation algorithm (FTA) for deconvolution computation, which well solves the computation imbalance problem and removes the extra memory requirement for overlapped partial sums. Besides, it can reduce the computation complexity for various types of deconvolutions significantly. Based on FTA, we develop a fast computing core (FCC) and the corresponding computing array so that the deconvolution can be efficiently computed. We next optimize the dataflow and storage scheme to further reuse on-chip memory and improve the computation efficiency. Finally, we present a computation-efficient hardware architecture for GANs and validate it on several GAN benchmarks, such as deep convolutional GAN (DCGAN), energy-based GAN (EBGAN), and Wasserstein GAN (WGAN). The experimental results show that our design can reach 2211 GOPS under 185-MHz working frequency on Intel Stratix 10SX field-programmable gate array (FPGA) board with satisfactory visual results. In brief, the proposed design can achieve more than 2× hardware efficiency improvement over previous designs, and it can reduce the storage requirement drastically.

Efficient reconfigurable architecture to enhance medical image security

Medical images are one of the most critical and sensitive types of data in information systems. For the secure storage and transfer of medical images, confidentiality is the most important aspect. This paper presents efficient embedding technique to enhance medical image security. The Gaussian filters are used as preprocessing to remove high frequency components and then applied to cumulative distribution function (CDF) 5/3 wavelet to obtain LL band features. Similarly, the LL band features of cover image are obtained. The alpha bending technique combines both the LL band features of cover and secret image to form first level of encryption and now with other high frequency bands of LH, HL and HH applied to Inverse CDF 5/3 obtains an encrypted image which is then transferred along with key obtained through other bands of LH, HL and HH. The key generated acts as additional level of security and similarly, at the receiver the opposite operations are performed to obtain the original secrete image. The performance is measured in terms of Peak signal-to-noise ratio (PSNR) and is compared with existing techniques to validate the results. Further, the entire architecture is synthesized on spartan 6 field-programmable gate array (FPGA) board to compare the hardware utilizations.

Automatic diseases detection and classification of EEG signal with pervasive computing using machine learning

PurposeThe natural control, feedback, stimuli and protection of these subsequent principles founded this project. Via properly conducted experiments, a multilayer computer rehabilitation system was created that integrated natural interaction assisted by electroencephalogram (EEG), which enabled the movements in the virtual environment and real wheelchair. For blind wheelchair operator patients, this paper involved of expounding the proper methodology. For educating the value of life and independence of blind wheelchair users, outcomes have proven that virtual reality (VR) with EEG signals has that potential.Design/methodology/approachIndividuals face numerous challenges with many disorders, particularly when multiple dysfunctions are diagnosed and especially for visually effected wheelchair users. This scenario, in reality, creates in a degree of incapacity on the part of the wheelchair user in terms of performing simple activities. Based on their specific medical needs, confined patients are treated in a modified method. Independent navigation is secured for individuals with vision and motor disabilities. There is a necessity for communication which justifies the use of VR in this navigation situation. For the effective integration of locomotion besides, it must be under natural guidance. EEG, which uses random brain impulses, has made significant progress in the field of health. The custom of an automated audio announcement system modified to have the help of VR and EEG for the training of locomotion and individualized interaction of wheelchair users with visual disability is demonstrated in this study through an experiment. Enabling the patients who were otherwise deemed incapacitated to participate in social activities, as the aim was to have efficient connections.FindingsTo protect their life straightaway and to report all these disputes, the military system should have high speed, more precise portable prototype device for nursing the soldier health, recognition of solider location and report about health sharing system to the concerned system. Field programmable gate array (FPGA)-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals, the soldier’s health is observed on systematic bases. By emerging Verilog hardware description language (HDL) programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t the whole work is approved in a Vivado Design Suite. Classification of different abnormalities and cloud storage of EEG along with the type of abnormalities, artifact elimination, abnormalities identification based on feature extraction, exist in the segment of suggested architecture. Irregularity circumstances are noticed through developed prototype system and alert the physically challenged (PHC) individual via an audio announcement. An actual method for eradicating motion artifacts from EEG signals that have anomalies in the PHC person’s brain has been established, and the established system is a portable device that can deliver differences in brain signal variation intensity. Primarily the EEG signals can be taken and the undesirable artifact can be detached, later structures can be mined by discrete wavelet transform these are the two stages through which artifact deletion can be completed. The anomalies in signal can be noticed and recognized by using machine learning algorithms known as multirate support vector machine classifiers when the features have been extracted using a combination of hidden Markov model (HMM) and Gaussian mixture model (GMM). Intended for capable declaration about action taken by a blind person, these result signals are protected in storage devices and conveyed to the controller. Pretending daily motion schedules allows the pretentious EEG signals to be caught. Aimed at the validation of planned system, the database can be used and continued with numerous recorded signals of EEG. The projected strategy executes better in terms of re-storing theta, delta, alpha and beta complexes of the original EEG with less alteration and a higher signal to noise ratio (SNR) value of the EEG signal, which illustrates in the quantitative analysis. The projected method used Verilog HDL and MATLAB software for both formation and authorization of results to yield improved results. Since from the achieved results, it is initiated that 32% enhancement in SNR, 14% in mean squared error (MSE) and 65% enhancement in recognition of anomalies, hence design is effectively certified and proved for standard EEG signals data sets on FPGA.Originality/valueThe proposed system can be used in military applications as it is high speed and excellent precise in terms of identification of abnormality, the developed system is portable and very precise. FPGA-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals the soldier health is observed in systematic bases. The proposed system is developed using Verilog HDL programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t and synthesised using in Vivado Design Suite software tool.

Implementation of a secure wireless communication system using true random number generator for internet of things

This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on the transmitter and receiver sides and were interfaced with Esp8266 chips to wirelessly send and receive encrypted sensor data. The MQ-2 gas sensor and tracking sensor were connected to the FPGA board on the transmitter side, where data from the sensors was encrypted using the exclusive-OR (XOR) function and the TRNG architecture. The system can be controlled by users through a web browser served by the ThingSpeak cloud. The Artix-7 FPGA device is used to implement the proposed wireless communication system, for which design and synthesis were done using the Xilinx Vivado 2015.2 tool. The proposed system uses a low amount of power and is suitable for a standalone, highly secure TRNG-based IoT application. The National Institute of Standard and Testing (NIST SP 800-22) test showed that ADPLL with finite impulse response (FIR) filter-based TRNGs are better for encrypting IoT devices for secure wireless communication.

CONTROL STRATEGY FOR REGENERATIVE BRAKING IN ELECTRIC VEHICLES

Abstract—In this paper, a high-speed 32-bit single precision Floating Point Unit (FPU) using Vedic mathematics is proposed. In a general processor, the division architecture plays a crucial role in deciding the overall speed of the system. However, the standard algorithms are sequential units and reduce the performance of the processor. Vedic Mathematics onthe other hand offers a new holistic approach to realizing these operations in a combinational unit. In the proposed architecture an optimized binary division architecture using Nikhilam Sutra is realized. The proposed method is coded in Verilog High Description Language (HDL), synthesized for Artix 7 Field-Programmable Gate Array (FPGA) board, and simulated using Xilinx Vivado Design Suite. Keywords:-Floating- points, Vedic maths, Nikhilam Sutra.

RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RT-libSGM runs more than 2× faster at a much lower energy cost.

Artificial TMAP Signal Generator Based on One-Bit Sigma Delta Modulator for MEC Test

The current study proposes three electrode-channels with time delay of artificial nerve signals generator utilized with only a active low pass filter and a Field Programmable Gate Array (FPGA). The XC3S100E FPGA board adopted to design a novel and real-time artificial transmembrane action potential (TMAP). The implementation of one bit Sigma Delta Modulation (SDM) method with linearized technique could be very expensive and complicated products with other technologies option currently available such as a microcontroller due to the fabrication requirements. This technique could employ in many biomedical applications and testing efficiently, especially, in evaluating the multi-electrode cuff system without requiring use of real nerves spike from animal models and saving time and effort, and cost. Moreover, this approach is adopted for further improvement to the signal performances such as resolution, accuracy, differential linearity monotonic DAC, and settling time of the signal waveform without extra hardware or cost required. In addition, the design included three channels of white Gaussian noise uncorrelated for each TMAP signal to simulate the real nerve noise environment, which surrounds the electrode cuff in experimental cases. A noise channels with adjustment level is added to the nerve spike using three sets of taps are employed to provide three channels of noise sources. The Xilinx ISE platform and Mentor Graphics ModelSim tool are used to simulate and implement this, and the results produced are compared. The power consumption of conventional technology is 31 mW, which is significantly higher than the power consumed (21mW) in modern technology. Furthermore, as compared to the usual way, the proposed solution conserved around 10% of the FPGA resources. This technique offers reuse in other applications where delay time, low amplitude voltage signals, and multichannel generator is needed. Moreover, this system offers adjustable waveform signal, noise level, conduction velocity and time delay easily to adequate different applications and tests.

FPGA–accelerated CNN for real-time plant disease identification

Using convolutional neural network (CNN) to identify plant diseases in-situ is a hot research topic in smart agriculture. Due to the memory-intensive and compute-intensive characteristics of CNN algorithm, it is difficult to implement CNN on edge terminals with limited memory and computational resources. In this paper, Field Programmable Gate Array (FPGA) is used to accelerate CNN to identify plant diseases. First, a 7-layer simple-structured network called “LiteCNN”, with only 176 K parameters and 78.47 M floating point operations (FLOPs) was designed. And knowledge distillation method was used to train LiteCNN, making that the accuracy reaches 95.24 %. Secondly, the acceleration circuit of LiteCNN was designed and implemented on “ZYNQ Z7-Lite 7020″ FPGA board. To compress the network and speed up plant disease identification, the following methods were applied: 1) Separable convolution took place of regular convolution, and a low-redundancy block convolution approach was used to load data; 2) The Batch Normalization (BN) layer was fused into the previous convolutional layer (or fully-connected layer); 3) Feature data and model parameters were expressed by half float data. As the basic function of the circuit achieved, methods including unrolling the for-loop, pipelining the for-loop, loop flattening and array partitioning were used to optimize the parallelism of the circuit. Finally, LiteCNN on the FPGA board was verified. The plant disease identification accuracy was 95.71 %, the inference speed was 0.071 s per frame, and the power consumption was 2.41 W. The results show that this paper proposed a low-power, high-accuracy and fast-speed plant disease identification terminal, which can be well applied for real-time plant disease identification in the field.

A Time-Modulated Antenna Array With Continuous Sideband Spectrum Distribution

Traditional time-modulated antenna arrays (TMAs) usually introduce sideband radiations at a multiple of discrete harmonic frequencies. To improve radiation efficiency of TMAs, various evolutionary algorithms become very popular in sideband suppressions. Apparently, the sideband radiation levels highly depend on the performance of these evolutionary algorithms. To achieve robust sideband suppression through physical designs, a novel pseudorandom hybrid phase–amplitude modulation technique is proposed to distribute the sideband radiation power over a continuous spectrum, rather than only at discrete harmonic frequencies. Following the law of energy conservation, sideband levels (SBLs) in this case naturally become extremely low, which eliminates the difficulty arising in TMAs’ sideband suppressions. Moreover, the novel modulation technique allows the synthesis of scanning beams with ultralow sidelobe levels, and the corresponding time modulation sequences could be directly calculated from analytical formulations. Therefore, evolutionary optimization algorithms are not necessary in the proposed TMA design procedure, which facilitates the real-time on-board calculation with an field-programmable gate array (FPGA) board. As compared with traditional TMAs, the proposed TMA achieves ultralow SBLs ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; -35.0$ </tex-math></inline-formula> dB) with much fewer time modulation statuses. Numerical and experimental results are presented to demonstrate the effectiveness of the proposed TMA.

MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application

The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

Faster-Than-Real-Time Hardware Emulation of Extensive Contingencies for Dynamic Security Analysis of Large-Scale Integrated AC/DC Grid

The rapid expansion of modern power systems has brought a tremendous computational challenge to dynamic security analysis (DSA) tools which consequently need to process extensive contingencies. In this work, hardware emulation is investigated to accelerate the DSA solution of a large-scale AC/DC system deployed on the field-programmable gate arrays (FPGAs) faster-than-real-time (FTRT) execution. Electromagnetic transient (EMT) modeling of the DC grid is conducted since the fast converter dynamics require a small time-step for accuracy; in contrast, the transient stability (TS) simulation is applicable to the AC grid which tolerates a much larger step size. To coordinate the 2 different types of simulation, an interface based on dynamic voltage injection is proposed to integrate the AC and DC grids, in addition to maintaining a low hardware latency. An emulation platform consisting of multiple FPGA boards is established so that with a proper allocation it has a sufficient capacity to accommodate the system under study which has 6 ACTIVSg 500-bus systems interconnected by a 6-terminal DC grid. The efficacy of the proposed FTRT hardware emulation platform is demonstrated by 2 case studies with more than 5500 contingencies analyzed in total, where an FTRT ratio of more than 208 is achieved for the hybrid AC/DC grid, while it is over 277 times for a single 500-bus system. Furthermore, the FTRT dynamic emulation results, including the security indices, are validated by the simulation tool DSATools/TSAT.

FPGA-oriented lightweight multi-modal free-space detection network

For autonomous vehicles, free-space detection is an essential part of visual perception. With the development of multi-modal convolutional neural networks (CNNs) in recent years, the performance of driving scene semantic segmentation algorithms has been dramatically improved. Therefore most free-space detection algorithms are developed based on multiple sensors. However, multi-modal CNNs have high data throughput and contain a large number of computationally intensive convolution calculations, limiting their feasibility for real-time applications. Field Programmable Gate Arrays (FPGAs) provide a unique combination of flexibility, performance, and low power for these problems to accommodate multi-modal data and the computational acceleration of different compression algorithms. Network lightweight methods offer great assurance for facilitating the deployment of CNNs on such resource-constrained devices. In this paper, we propose a network lightweight method for a multi-modal free-space detection algorithm. We first propose an FPGA-friendly multi-modal free-space detection lightweight network. It comprises operators that FPGA prefers and achieves a 95.54 % MaxF score on the test set of KITTI-Road free-space detection tasks and 81 ms runtime when running on 700 W GPU devices. Then we present a pruning approach for this network to reduce the number of parameters in case the complete model exceeds the FPGA chip memory. The pruning is in two parts. For the feature extractors, we propose a data-dependent filter pruner according to the principle that the low-rank feature map contains less information. To not compromise the integrity of the multi-modal information, the pruner is independent for each modality. For the segmentation decoder, we apply a channel pruning approach to remove redundant parameters. Finally, we implement our designs on an FPGA board using 8-bit quantisation, and the accelerator achieves outstanding performance. A real-time application of scene segmentation on KITTI-Road is used to evaluate our algorithm, and the model achieves a 94.39 % MaxF score and minimum 14 ms runtime on 20W FPGA devices.

Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system–sliding mode observer for direct torque control of induction motor drive

This article aims first to propose an improved space vector modulation–direct torque control in order to enhance the induction motor performance using: (1) a super-twisting controller and (2) a novel model reference adaptive system based on a sliding mode observer. Second, due to the complexity of the suggested control algorithm, this article deals also with a hardware implementation on a field-programmable gate array board. Indeed, the field-programmable gate array is mainly chosen to reduce the execution time, thanks to its parallel processing which significantly improves the quality of the control system by reducing the sampling period, and consequently the delays in the control loop. Besides, the super-twisting controller is proposed to enhance the speed regulation loop which is a second-order sliding mode control technique that uses a continuous control law to prevent the chattering phenomenon induced by the first-order sliding mode control technique. Moreover, the high performance control requires information about the rotor speed which can be obtained by a sensor. Generally, the use of the speed sensor increases the system cost and size, and reduces its system reliability. Therefore, a combination between a model reference adaptive system observer and a sliding mode observer is suggested for speed estimation and overcoming the sensitivity of the classical model reference adaptive system observer against uncertainties and stator resistance variations. The performance of the proposed space vector modulation--direct torque control--super-twisting controller with the model reference adaptive system--sliding mode observer algorithm of an induction motor is verified through simulation, hardware co-simulation and experimental validation utilizing a field-programmable gate array Virtex-5-ML507 board. The performance of the suggested sensorless control method is compared also with other recent published schemes.

Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol

&lt;span lang="EN-US"&gt;Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the &lt;a name="_Hlk107307233"&gt;&lt;/a&gt;universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.&lt;/span&gt;

An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks

This article proposes an uninterrupted processing technique for the convolutional neural network (CNN) accelerator. It primarily allows the CNN accelerator to simultaneously perform both processing element (PE) operation and data fetching that reduces its latency and enhances the achievable throughput. Corresponding to the suggested technique, this work also presents a low latency VLSI-architecture of the CNN accelerator using the new random access line-buffer (RALB)-based design of PE array. Subsequently, the proposed CNN-accelerator architecture has been further optimized by reusing the local data in PE array, incurring better energy conservation. Our CNN accelerator has been hardware implemented on Zynq-UltraScale + MPSoC-ZCU102 FPGA board, and it operates at a maximum clock frequency of 340 MHz, consuming 4.11 W of total power. In addition, the suggested CNN accelerator with 864 PEs delivers a peak throughput of 587.52 GOPs and an adequate energy efficiency of 142.95 GOPs/W. Comparison of aforementioned implementation results with the literature has shown that our CNN accelerator delivers 33.42% higher throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.24\times $ </tex-math></inline-formula> better energy efficiency than the state-of-the-art work. Eventually, the field-programmable gate array (FPGA) prototype of the proposed CNN accelerator has been functionally validated using the real-world test setup for the detection of object from input image, using the GoogLeNet neural network.

Secure lightweight cryptosystem for IoT and pervasive computing

Large volumes of sensitive data are being transferred among devices as the Internet of Things (IoT) grows in popularity. As a result, security measures must be implemented to ensure that unauthorized parties do not obtain access to the data. It is well acknowledged that IoT devices have restricted resources, such as limited battery life, memory, and hence reaction time. Classical encryption approaches and methods become inefficient for IoT devices due to memory limits. Large volumes of sensitive data are being transferred between devices as the Internet of Things (IoT) grows in popularity. This involves the implementation of security safeguards to ensure that unauthorized parties do not obtain access to the data. IoT devices are notorious for having limited resources, such as battery life, memory, and hence response time. Classical encryption approaches and methods become inefficient for IoT devices due to memory limits. As a result, a Lightweight cryptosystem that fits the needs of Lightweight devices and ubiquitous computing systems has emerged. The goal of this study is to present a Lightweight cryptosystem (LWC) that may be used as a plugin to secure data transfers in IoT devices and pervasive computing. To that goal, the researchers employ several simple measuring techniques. The suggested system was then implemented on a field-programmable gate array (FPGA) board using the Verilog programming language to demonstrate its appropriateness for actual security applications. FPGA is also utilized in hardware applications to assess the system’s resource usage and performance. Finally, a comparison of the proposed system with previous lightweight cryptography systems is performed to reinforce the major goal of this work, which is to present a new lightweight cryptosystem.

Efficient Homomorphic Convolution Designs on FPGA for Secure Inference

Recently, secure neural network (NN) inference, a combination of homomorphic encryption (HE) and NN, has attracted much attention. Nevertheless, a large number of computations, mainly brought by the HE scheme, form the bottleneck in real-time applications. In this article, we present a hardware accelerator on a field-programmable gate array (FPGA) for the homomorphic convolution layer (HomConvL), which is the most computation-intensive part of the HE-based secure inference. First, we propose a new HomConvL algorithm called packed rotations at inputs (PaRotI), which is suitable for hardware implementation for its inherent high parallelism and low complexity with acceptable noise growth and moderate resource consumption. Then, we present three highly parallel architectures for different parameter sets and application scenarios of state-of-the-art HomConvL algorithms. The new architectures are implemented on a Xilinx VCU110 FPGA board, and the experimental results demonstrate that our designs can achieve 15.31– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.46\times $ </tex-math></inline-formula> speedups compared with the software implementations.

Diabetes Prediction Tool under System on Chip Using Machine Learning Method

Extraordinary advances in biotechnology and health sciences have brought significant generation of data, such as genetic data and clinical information, generated from huge electronic health records. Data analysis is a process of studying and identifying hidden patterns from large amounts of data and drawing conclusions. In health care, this analytical process is carried out using machine learning (ML) algorithms to analyze medical data to build Machine Learning models to transform all available information into valuable knowledge. Nowadays, diabetes has become a common disease among young people, elderly people, and even children. According to the World Health Organization (WHO) report, by 2025, this number is expected to exceed 380 million. This research work performs a comparison of 5 classification techniques, namely Naive Bayes (NB), Bagging (J48), Decision Tree (J48, C4.5), K Nearest Neighbors (KNN), and Support Vector Machine (SVM), to detect diabetes at an early stage. The performances of the five algorithms are evaluated and compared on various measures like accuracy, precision, and recall. The experiments were conducted based on the diabetes database, the source from the National Institute of Diabetes, Digestive and Kidney Diseases, showing the effectiveness of using the Decision Tree (DT) technique. This effectiveness led to the choice of this method. After obtaining the DT model of the problem, the main task facing us in this work is the hardware implementation of this model. Indeed, this forecasting system can be used in other complementary works as a processing unit in a cloud, to be able to manage numerous requests. The considered solution is the hardware implementation on a Field Programmable Gate Array (FPGA) board.

Real-time post-processing for physical-layer secure key distribution in fiber networks

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double-threshold quantization, information reconciliation (IR) with Bose–Chaudhuri–Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.