Field Of High Performance Computing Research Articles

Mathematical Analysis for GPU Framework for High Performance Computing with Improved Scalability, Reliability and Seamless Configurability

In the field of High Performance Computing (HPC), which is changing very quickly, using Graphics Processing Units (GPUs) has become essential for getting a lot of computing power and speed. This study gives a thorough mathematical analysis of a GPU system that is meant to improve scalability, stability, and configurability, all of which are very important for next-generation HPC apps. The suggested framework uses complex mathematical models and methods to make the best use of GPU resources, cut down on delay, and guarantee strong performance across a wide range of tasks. Scalable parallel processing methods are built into the framework so it can adapt to changing computing needs, making the most of speed and resource use. Fault-tolerant methods that lessen the effects of hardware breakdowns and computing mistakes also improve reliability, making sure that results are always correct and consistent. The framework can be set up in different ways because it is based on flexible design, which makes it easy to change and adapt to the needs of each application without affecting speed. In diverse computer settings, where different apps may have different working needs, this ability to change is very important. The mathematical analysis includes performance measures like speed, delay, and mistake rates, which give a solid basis for judging how well the system works. Additionally, tests comparing the suggested system to current GPU tools show that it is more reliable and scalable. This study helps make better, more reliable computer systems by looking at some of the biggest problems in GPU-based high-performance computing. The results show that using this method can greatly improve the skills of HPC systems, which can lead to progress in scientific study, data analysis, and complex models. In the end, this work shows how advanced GPU systems can help drive innovation in HPC, leading to more powerful, reliable, and flexible computing options.

First Impressions of the Sapphire Rapids Processor with HBM for Scientific Workloads

The landscape of high performance computing (HPC) has witnessed exponential growth in processor diversity, architectural complexity, and performance scalability. With an ever-increasing demand for faster and more efficient computing solutions to address an array of scientific, engineering, and societal challenges, the selection of processors for specific applications becomes paramount. Achieving optimal performance requires a deep understanding of how diverse processors interact with diverse workloads, making benchmarking a fundamental practice in the field of HPC. Here, we present preliminary results observed over such benchmarks and applications and a comparison of Intel Sapphire Rapids and Skylake-X, AMD Milan, and Fujitsu A64FX processors in terms of runtime performance, memory bandwidth utilization, and energy consumption. The examples focus specifically on the Sapphire Rapids processor with and without high-bandwidth memory (HBM). An additional case study reports the performance gains from using Intel’s Advanced Matrix Extensions (AMX) instructions, and how they along with HBM can be leveraged to accelerate AI workloads. These initial results aim to give a rough comparison of the processors rather than a detailed analysis and should prove timely and relevant for researchers who may be interested in using Sapphire Rapids for their scientific workloads.

DIFFERENCE BETWEEN OPENHPC AND HTCONDOR CLUSTER SYSTEMS: IN-DEPTH ANALYSIS

The rapidly developing field of high-performance computing (HPC) requires efficient and scalable solutions to manage extensive computing loads. Although they use different approaches and architectures, OpenHPC and HTCondor are well-known platforms that meet these needs. This article thoroughly analyzes OpenHPC and HTCondor to identify their fundamental differences and work paradigms. OpenHPC is a comprehensive modular structure designed to facilitate the deployment, management, and maintenance of HPC clusters, offering a rich set of pre-integrated HPC software components. Conversely, HTCondor specializes in efficiently planning and managing resource-intensive tasks, using a unique partner selection system for dynamic resource allocation based on job requirements and resource availability. By examining aspects such as system architecture, resource management efficiency, scalability, flexibility, and the user ecosystem, this analysis sheds light on the strengths and weaknesses of each structure. The research aims to provide stakeholders in high-performance computing with the knowledge necessary to make informed decisions regarding the selection and implementation of high-performance computing management systems, ultimately aimed at optimizing the use of computing resources and optimizing research and development workflows.

Program partitioning and deadlock analysis for MPI based on logical clocks

The message passing interface (MPI) has become a standard for programming models in the field of high performance computing. It is of great importance to ensure the reliability of MPI programs by detecting whether there exist errors in them. However, as one of the most common errors in MPI programs, deadlock is difficult to detect due to the non-determinism and the asynchronous communication supported by MPI. Existing approaches mainly focus on detecting deadlocks by traversing all possible execution paths in an MPI program. But in this way the detection efficiency is always limited since the number of execution paths increases exponentially with the number of wildcard receives and processes in the program.In order to alleviate the path explosion problem for single-path MPI programs, we propose a program partitioning approach based on logical clocks to detecting deadlocks. In the approach, the program is first divided into several preliminary partitions based on the matching detection rule. Then to obtain the dependency relationships of partitions, the Binary Lazy Clocks algorithm is raised to mark clocks for communication operations. Based on the clocks, the completion orders of communication operations in each process of the program are tracked. Further, we get the dependency relationships of the preliminary partitions by analyzing these completion orders and merge the preliminary partitions with the dependency relationships for generating the final partitions. Finally, deadlocks are detected by traversing all possible execution paths of each final partition. We have implemented our method in a tool called PDMPI and performed experimental evaluation on 14 programs. The experimental results indicate that PDMPI is more effective for detecting deadlocks in MPI programs than two most related tools ISP and SAMPI, especially in programs with numerous interleavings.

Introduction to High-Performance Computing.

Since the first general-purpose computing machines came up in the middle of the twentieth century, computer science's popularity has been growing steadily until our time. The first computers represented a significant leap forward in automating calculations, so that several theoretical methods could be taken from paper into practice. The continuous need for increased computing capacity made computers evolve and become more and more powerful. Nowadays, high-performance computing (HPC) is a crucial component of scientific and technological advancement. This book chapter introduces the field of HPC, covering key concepts and essential terminology to understand this complex and rapidly evolving area. The chapter begins with an overview of what HPC is and how it differs from conventional computing. It then explores the various components and configurations of supercomputers, including shared memory systems, distributed memory systems, and hybrid systems and the different programming models used in HPC, including message passing, shared memory, and data parallelism. Finally, the chapter discusses significant challenges and future directions in supercomputing. Overall, this chapter provides a comprehensive introduction to the world of HPC and is an essential resource for anyone interested in this fascinating field.

Optimization Techniques for GPU Programming

In the past decade, Graphics Processing Units have played an important role in the field of high-performance computing and they still advance new fields such as IoT, autonomous vehicles, and exascale computing. It is therefore important to understand how to extract performance from these processors, something that is not trivial. This survey discusses various optimization techniques found in 450 articles published in the last 14 years. We analyze the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.

Integrating parallelism and asynchrony for high-performance software development

This article delves into the crucial roles of parallelism and asynchrony in the development of high-performance software programs. It provides an insightful exploration into how these methodologies enhance computing systems' efficiency and performance. The discussion begins with an overview of high-performance programs and their importance in modern computing, followed by a detailed analysis of parallelism, including its hardware and software aspects, various programming models, and diverse applications in fields like computational tasks, data processing, and machine learning. The article then shifts focus to asynchrony, elaborating on its implementation through callback functions, promises, and the async/await syntax. It highlights the significant benefits of asynchrony in improving program responsiveness and efficiency, especially in I/O-bound and network-intensive operations. A critical section of the article examines the combined application of parallelism and asynchrony in different domains, notably in Graphics Processing Unit (GPU) computations, distributed systems, and web development. This combination is shown to be particularly effective in handling Big Data, where rapid and efficient data processing is essential. The article concludes by emphasizing the indispensable nature of these approaches in modern software development. Parallelism and asynchrony are not merely performance enhancement tools but are fundamental in building innovative, resilient, and scalable software solutions. This comprehensive exploration underscores the ongoing relevance of these methodologies and their potential to drive further advancements in the field of high-performance computing.

Translating High-Performance Computing Tools From Research to Practice: Experiences With the TAU Performance System

The field of high-performance computing (HPC) has always challenged the research community to design and develop performance observation technology (based on instrumentation, measurement, and analysis methods), keeping pace with the rapid and aggressive evolution of HPC systems’ hardware and software. While the scope of observational concerns is broad and complex, it is the HPC innovation flux that poses difficult translation issues, even for performance tools of limited functionality. Both the complexity of HPC performance observation and the HPC translational pressures have kept the performance tools community mostly research oriented, with only a few open source toolkits widely used. The TAU Performance System is a performance toolkit for HPC with more than 30 years of continuous research and development. This project at the University of Oregon has attempted to keep TAU at the forefront of performance observation capabilities, ported to the latest HPC platforms available, and supported by a dedicated core research team. This article briefly describes the project’s research work and the challenges encountered, with a particular emphasis on the translation process necessary to make TAU the leading performance technology it is today.

Shape optimization of hotspot targeted micro pin fins for heterogeneous integration applications

In the field of high-performance computing (HPC), growing power demands makes Heterogeneous Integration (HI) the future of next-generation computing systems to sustain Moore's law. HI refers to the assembly of different separately-manufactured components onto a single electronic module to enhance functionality and operating characteristics. As a consequence of HI, the next generation of electronic chips have regions of localized hotspots or cores, translating to a region of extremely high temperature if not adequately cooled. The mitigation of hotspots demands advanced thermal management cooling schemes compared to the conventional ones. This study investigates the combination of impingement jet array of liquid water and non-uniform hotspot targeted micro pin fins, printed on chips, as a potential heat transfer augmentation technique. The configuration comprises four 2cm×2cm chips (Total chip area is 16 cm2) with eight hotspots on each. Liquid water is employed as the coolant in the present study. A detailed numerical parametric study and optimization were carried out using a supervised machine learning algorithm. The multi-objective optimization is performed to optimize both the thermal and flow resistances simultaneously. The results from the detailed optimization reveal that optimal fin parameters for the regions of hotspot and background could be significantly different. The optimal pin fin configuration resulted in a minimum thermal resistance of 0.208 K.cm2/W (0.013K/W) at a constrained pressure drop of about 10 kPa.

Scalable epidemic message passing interface fault tolerance

Resilience and fault tolerance are challenging tasks in the field of high performance computing (HPC) and extreme scale systems. Components fail more often in such systems, results in application abort. Adopting fault–tolerance techniques can be consistently detect failures and continue application’s execution even if the failures exist. A prominent parallel programming specification, message passing interface (MPI), as it would be used to implement failure detection and consensus algorithm in this paper. Although the MPI does not facilitate fault tolerant behavior, this work presents a fault tolerant, matrix based failure detection and consensus algorithm. The proposed algorithm uses Gossiping. To detect failures, randomised pinging will be applied during the execution of the algorithm by using piggybacked gossip messages. In order to achieve consensus on the failures in the system, failed processes’ information will be sent using the same piggybacked gossip messages to all the alive processes. The algorithm was implemented in MPI framework and is completely fault tolerant. The results exhibit all the MPI process failures were detected using randomised pinging and global consensus has achieved on failed MPI process in the system.

Approximate Computing [The Editors’ Desk

Computing has been at the core of the Digital Revolution (also known as the Third Industrial Revolution) since the latter half of the 20th century. Progress on approximate computing has been promising for data storage and processing associated with recent advancements in artificial intelligence and big data. It is our great pleasure to introduce the guest editors of this special issue of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Nanotechnology Magazine</i> on approximate computing: Dr. Jie Han and Dr. Weiqiang Liu, who are experts in the field of high-performance computing, and Prof. Shao-Ku Kao, Chang Gung University, and Prof. Toshiya Sakata, University of Tokyo, serve as associate editors for this special issue. We hope the readers will greatly enjoy it.

The Future Role of High-Performance Computing in Cardiovascular Medicine and Science -Impact of Multi-Dimensional Data Analysis.

Advances in High-performance computing (HPC) technology have reached the capacity to inform cardiovascular (CV) science in the realm of both inductive and constructive approaches. Clinical trials allow for the comparison of the effect of an intervention without the need to understand the mechanism. This is a typical example of an inductive approach. In the HPC field, training an artificial intelligence (AI) model, constructed by neural networks, to predict future CV events with the use of large scale multi-dimensional datasets is the counterpart that may rely on as well as inform understanding of mechanistic underpinnings for optimization. However, in contrast to clinical trials, AI can calculate event risk at the individual level and has the potential to inform and refine the application of personalized medicine. Despite this clear strength, results from AI analyses may identify otherwise unidentified/unexpected (i.e. non-intuitive) relationships between multi-dimensional data and clinical outcomes that may further unravel potential mechanistic pathways and identify potential therapeutic targets, therebycontributing to the parsing of observational associations from causal links. The constructive approach will remain critical to overcome limitations of existing knowledge and anchored biases to actualize a more sophisticated understanding of the complex pathobiology of CV diseases. HPC technology has the potential to underpin this constructive approach in CV basic and clinical science. In general, even complex biological phenomena can be reduced to combinations of simple biological/chemical/physical laws. In the deductive approach, the focus/intent is to explain complex CV diseases by combinations of simple principles.

Traffic and overhead analysis of applied pre-filtering ACL firewall on HPC service network

In an high-performance computing (HPC), supercomputing service environment, the security of infrastructure nodes that are points of contact for researchers is very important. We have applied various security devices such as anti-DDoS, IPS, firewall, web application firewall, and etc. on an HPC service network to provide more secure supercomputing services. Firewalls are a common and essential element of network security devices with the ability to block network traffic according to pre-defined rules. With the increasing demands for services, cyberattacks, as well as overheads on firewall policies have also increased. To reduce this overhead, in our previous research, we analyzed dropped packets log and performed a method on the firewall as Abnormal IP that can detect and deny anomalous IPs in real-time. As the number of abnormal IPs increased, the performance of the firewall significantly deteriorated. To solve this problem, we applied access control list (ACL) at the front-end of the firewall to perform pre-filtering, thereby improving the performance of the firewall on the HPC service network. This research is expected to contribute as a preliminary study in the HPC field by deriving pre-filtering ACL to reduce the CPU load of firewall server by showing the result of about 21.5% improvement in performance.

Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

The heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49times and achieves an energy saving of 5.16times on average.

RETRACTED ARTICLE: Multimedia music education based on adaptive genetic algorithm and heterogeneous processors

Various factors in the stock market are intricate and complex, and changes in the primary and secondary relationship are uncertain. The investigation found that the stock price is affected by factors such as buyers and sellers, stock policies, investors and other factors. Considering these factors, it is easy to draw a conclusion: stock price changes are random. After understanding the most obvious characteristics of stock prices, I found that there are very few high-precision stock price prediction models in the market. Under this background, it is necessary to study high-precision stock price prediction models. After looking up information from multiple parties, the method chosen by the author is a new method formed by the combination of BP neural network and genetic algorithm. The investigation found that the random initial weight of BP neural network and genetic algorithm will enter an infinite loop due to the local optimal solution. The author made some improvements, because adaptive genetic algorithm can solve the problem of initial weight of BP neural network, so BP The neural network is improved by an adaptive genetic algorithm, and a high-precision stock prediction model can be obtained. Heterogeneous processors are increasingly used in the field of high-performance computing, especially in the application of processor cores, which provides huge potential for parallel computing, but it also brings huge challenges. Higher accuracy requires a large knowledge system and a more advanced programming model. People need to master a more advanced programming model. Because for most programmers, this requirement is almost impossible to complete, so I thought of another way, using parallel compilation to complete the work. At present, the parallel compilation technology for heterogeneous architecture has achieved fruitful research results, but there are still many problems that need to be analyzed and solved. For these problems, the author proposes to create a new data area that transfers data to the nested external calculation, so the data transfer only occurs before and after the loop calculation, thereby avoiding the internal parallel loop in the iterative calculation process. Multiple copies of external serial loop data. Experiments show that these storage optimization methods can optimize the transmission, storage and access of different levels and different granularities of data, thereby improving the performance of the generated parallel programs to varying degrees.

Developing a Model for Holistic Workload Analysis of Large Supercomputer Systems

Any modern supercomputer has an extremely complex architecture, and efficient usage of its resources is often a very difficult task, even for experienced users. At the same time, the field of high-performance computing is becoming more and more in demand, so the issue of efficient utilization of supercomputers is very urgent. Therefore, users should know everything important about performance of their jobs running on a supercomputer in order to be able to optimize them, and administrators should be able to monitor and analyze all the nuances of the efficient functioning of such systems. However, there is currently no complete understanding of what data are best to be studied (and how it should be analyzed) in order to have a whole picture of the state of the supercomputer and the processes taking place there. In this paper, we make our first attempt to answer this question. To do this, we are developing a model that describes all the potential factors that may be important when analyzing the performance of supercomputer applications and the HPC system as a whole. The paper provides both a detailed description of this model for users and administrators and some interesting real-life examples discovered on the Lomonosov-2 supercomputer using a software implementation based on the proposed model. Любой современный суперкомпьютер имеет крайне сложную архитектуру, и эффективное использование его ресурсов зачастую является очень сложной задачей даже для опытных пользователей. В то же время высокопроизводительные вычисления становятся все более востребованными и вопрос эффективного использования суперкомпьютеров очень актуален. Поэтому пользователи должны знать все самое важное о производительности их работы, выполняемой на суперкомпьютере, чтобы иметь возможность ее оптимизировать, а администраторы должны уметь отслеживать и анализировать все нюансы эффективного функционирования таких систем. Однако в настоящее время нет полного понимания того, какие данные лучше всего для этого изучать (и как их следует анализировать), чтобы иметь полную картину состояния суперкомпьютера и происходящих на нем процессов. В этой статье мы делаем нашу первую попытку ответить на этот вопрос. Для этого мы разрабатываем модель, которая описывает все потенциальные факторы, которые могут быть важными при анализе производительности суперкомпьютерных приложений и системы HPC в целом. В документе представлено как подробное описание этой модели для пользователей и администраторов, так и несколько интересных реальных примеров, обнаруженных на суперкомпьютере Ломоносов-2 с помощью программного обеспечения, реализованного на основе предложенной модели.

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

Dynamically partially reconfigurable (DPR) technology based on FPGA is applied extensively in the field of high-performance computing (HPC) because of its advantages in processing efficiency and power consumption. To make full use of the advantages of DPR in execution efficiency, we build a DPR system model that meets to the actual application requirements and the objective constraints. According to the consistency of reconfiguration order and dependencies, we propose two algorithms based on simulated annealing (SA). The algorithms partition FPGA resource to several regions and schedule tasks to the regions. In order to improve the performance of the algorithms, we exploit the module merging technology to improve the parallelism of task execution and design a new solution generation method to speed up the convergence speed. Experimental results show that the proposed algorithms have a lower time complexity than mixed-integer linear programming (MILP), iterative scheduler (IS) and Ant Colony Optimization (ACO). For applications with more tasks, the proposed algorithms show performance advantages in producing better partitioning and scheduling results in a shorter time.

Autotuning based on frequency scaling toward energy efficiency of blockchain algorithms on graphics processing units

Energy-efficient computing is especially important in the field of high-performance computing (HPC) on supercomputers. Therefore, automated optimization of energy efficiency during the execution of a compute-intensive program is desirable. In this article, a framework for the automatic improvement of the energy efficiency on NVIDIA GPUs (graphics processing units) using dynamic voltage and frequency scaling is presented. As application, the mining of crypto-currencies is used, since in this area energy efficiency is of particular importance. The framework first determines the energy-optimal frequencies for each available currency on each GPU of a computer automatically. Then, the mining is started, and during a monitoring phase it is ensured that always the most profitable currency is mined on each GPU, using optimal frequencies. Tests with different GPUs show that the energy efficiency, depending on the GPU and the currency, can be increased by up to 84% compared to the usage of the default frequencies. This in turn almost doubles the mining profit.

PREFACE

It is with great pleasure that I introduce the proceedings of the 2019 High Performance Computing and Computational Intelligence Conference (HPCCI 2019) which was held recently Chengdu, China during October 25-27, 2019. HPCCI 2019 was dedicated to technical issues related to High Performance Computing and Computational Intelligence.High performance computing represents the national strength of a country and plays an essential supporting role in the development of national science and technology. Quantum computing, as a new computing method, could be an emerging area of high-performance computing in the future. The development of high performance computing may have some breakthroughs in these areas. At the same time, it is found that the implicit parallelism provided by the quantum system improves the performance of the algorithm. Quantum theory may be an important research direction to construct the basic theoretical system for some intelligence schemes in the future. The development of computational intelligence cannot be separated from the support of high-performance computing. The development of the two subject areas has gradually formed an integrated system. Based on it, the objectives of the conference were not only to provide opportunities to the international scientists to present state of the art research in High Performance Computing and Computational Intelligence but also to provide a forum to discuss ideas for future directions in the field and explore possibilities for collaborative research projects.The conference program included keynote, oral, and poster presentations from scholars working in the areas of High Performance Computing and Computational Intelligence from all over the world. It covered recent trends and progress made in the field of High Performance Computing and Computational Intelligence. Keynote lectures regarding the latest information in their respective areas of expertise were shared by experts.The proceedings present a selection of high quality papers submitted to the conference by researchers from universities, research institutes, and industry. All papers were subjected to peer-review by conference committee members and international reviewers. The papers were selected based on their quality and their relevance to the conference. The proceedings present recent advances in the fields of High performance Computing and Computing Intelligence.I would like to express special gratitude to members of the conference committee and organizers of the conference. I would also like to thank the reviewers for their valuable time and advice which helped in improving the quality of the papers selected for presentation at the conference and for publication in the proceedings. Finally I want to thank the authors, the members of the organizing committee, the reviewers, the chairpersons, sponsors, and all other conference participants for their support of HPCCI 2019.Conference ChairProf. Peng Wang Southwest Minzu University, China

Applying model-driven engineering to high-performance computing: Experience report, lessons learned, and remaining challenges

Abstract Thanks to the increasing power of supercomputers, CEA develops ever more complex numerical simulators in the field of High Performance Computing (HPC) to cover a wide range of physical phenomena. As a consequence, simulation codes tend to become unmanageable and difficult to maintain and adapt to new hardware architectures. In this paper, we report on our experience in the use of Model-Driven Engineering (MDE) and Domain-Specific Languages (DSLs) to face these challenges through two projects, namely Modane and NabLab. From this experience, we discuss the main lessons learned to be considered for conducting future projects in the field of HPC, and the remaining challenges that are worth being included in the road-map of the MDE community.