Field Of High Performance Computing Research Articles

GPUs Outperform Current HPC and Neuromorphic Solutions in Terms of Speed and Energy When Simulating a Highly-Connected Cortical Model.

While neuromorphic systems may be the ultimate platform for deploying spiking neural networks (SNNs), their distributed nature and optimization for specific types of models makes them unwieldy tools for developing them. Instead, SNN models tend to be developed and simulated on computers or clusters of computers with standard von Neumann CPU architectures. Over the last decade, as well as becoming a common fixture in many workstations, NVIDIA GPU accelerators have entered the High Performance Computing field and are now used in 50 % of the Top 10 super computing sites worldwide. In this paper we use our GeNN code generator to re-implement two neo-cortex-inspired, circuit-scale, point neuron network models on GPU hardware. We verify the correctness of our GPU simulations against prior results obtained with NEST running on traditional HPC hardware and compare the performance with respect to speed and energy consumption against published data from CPU-based HPC and neuromorphic hardware. A full-scale model of a cortical column can be simulated at speeds approaching 0.5× real-time using a single NVIDIA Tesla V100 accelerator—faster than is currently possible using a CPU based cluster or the SpiNNaker neuromorphic system. In addition, we find that, across a range of GPU systems, the energy to solution as well as the energy per synaptic event of the microcircuit simulation is as much as 14× lower than either on SpiNNaker or in CPU-based simulations. Besides performance in terms of speed and energy consumption of the simulation, efficient initialization of models is also a crucial concern, particularly in a research context where repeated runs and parameter-space exploration are required. Therefore, we also introduce in this paper some of the novel parallel initialization methods implemented in the latest version of GeNN and demonstrate how they can enable further speed and energy advantages.

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

Not only in the field of high-performance computing (HPC), field programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to central processing units (CPUs) or even graphics processing units (GPUs), adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096[Formula: see text]4096 and solution on the coarsest using the conjugate gradient (CG) method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

Prediction of drug solubility on parallel computing architecture by support vector machines

Recent great advances in the field of high-performance computing offer new opportunities in bioinformatics, computational chemistry, and computational biology. In this paper, we use the computational methods, for instance, the support vector machines (SVM) to optimize the prediction of solubility of compounds. SVMs are trained with known data of soluble and insoluble compounds of a database, and such information is subsequently used to improve the prediction obtained by virtual screening technique. The use of larger databases increases the probability generating leads or hits, the necessary calculation time increases with the volume of the database and the accuracy of virtual screening methods. We discuss the benefits of the use of massively parallel architectures, in particular, the graphics processing units. We empirically demonstrate that the graphics processing units are well adapted for the methodical acceleration of the support vector machines, of the order up to 45 times, compared to their sequential version.

An inventive high-performance computing electronic information system for professional postgraduate training

ABSTRACTElectronic information professional postgraduate training is the mixed learning strategy used in the present educational era for a better utilization of e-resources in the field like data mining and data handling fields to develop a high-performance computing (HPC) systems which are quite inventive and useful to the society. The principle of combining the innovation practice in computing field is applicable in all teaching methodologies to provide a better training method to the mankind. The research is performed using statistical data collected from postgraduate students of 200 members in an educational institution and a correlation coefficient is used to calculate the hypothesis present in the survey. Inventive design based on theory of inventive problem solving is used to solve the classical problematic situations which will arise in the conflict on uncertain information. The purpose of research is to find the ways to recommend the methods to create active awareness in electronic information literacy for improvement of better utilization of resources. This research work addresses the issues in postgraduate training modes and the opportunities present in the HPC field.

VBMq: pursuit baremetal performance by embracing block I/O parallelism in virtualization

Barely acceptable block I/O performance prevents virtualization from being widely used in the High-Performance Computing field. Although the virtio paravirtual framework brings great I/O performance improvement, there is a sharp performance degradation when accessing high-performance NAND-flash-based devices in the virtual machine due to their data parallel design. The primary cause of this fact is the deficiency of block I/O parallelism in hypervisor, such as KVM and Xen. In this paper, we propose a novel design of block I/O layer for virtualization, named VBMq. VBMq is based on virtio paravirtual I/O model, aiming to solve the block I/O parallelism issue in virtualization. It uses multiple dedicated I/O threads to handle I/O requests in parallel. In the meanwhile, we use polling mechanism to alleviate overheads caused by the frequent context switches of the VM’s notification to and from its hypervisor. Each dedicated I/O thread is assigned to a non-overlapping core to improve performance by avoiding unnecessary scheduling. In addition, we configure CPU affinity to optimize I/O completion for each request. The CPU affinity setting is very helpful to reduce CPU cache miss rate and increase CPU efficiency. The prototype system is based on Linux 4.1 kernel and QEMU 2.3.1. Our measurements show that the proposed method scales graciously in the multi-core environment, and provides performance which is 39.6x better than the baseline at most, and approaches bare-metal performance.

System-wide trade-off modeling of performance, power, and resilience on petascale systems

While performance remains a major objective in the field of high-performance computing (HPC), future systems will have to deliver desired performance under both reliability and energy constraints. Although a number of resilience methods and power management techniques have been presented to address the reliability and energy concerns, the trade-offs among performance, power, and resilience are not well understood, especially in HPC systems with unprecedented scale and complexity. In this work, we present a co-modeling mechanism named TOPPER (system-wide Trade-Off modeling for Performance, PowEr, and Resilience). TOPPER is build with colored Petri nets which allow us to capture the dynamic, complicated interactions and dependencies among different factors such as workload characteristics, hardware reliability, runtime system operation, on a petascale machine. Using system traces collected from a production supercomputer, we conducted a series of experiments to analyze various resilience methods, power capping techniques, and job characteristics in terms of system-wide performance and energy consumption. Our results provide interesting insights regarding performance–power–resilience trade-offs on HPC systems.

Dual buffer rotation four-stage pipeline for CPU–GPU cooperative computing

Accelerators such as GPUs have become popular general-purpose computing device in the field of high-performance computing. With the boosting ability of storage and computation, it is very important to solve the complex scientific and engineering problems on CPU–GPU heterogeneous system in the big data era. Now the compute-intensive problems have been successfully solved using CPU–GPU cooperative computing. However, it is difficult to handle large-scale data-intensive problems, especially for those limited by GPU device memory. In this paper, the dual buffer rotation four-stage pipeline (DBFP) mechanism is proposed for CPU–GPU cooperative computation to efficiently handle data-intensive problems, which need larger memory than that of a single GPU. The data block partition-based pipeline computing strategy is designed on top of the DBFP mechanism. On the one hand, it breaks out the bottleneck of limited GPU device memory. On the other hand, it explores high-performance computing of CPU and GPU with data transfer and computation overlap. Furthermore, it is easy to extend the DBFP mechanism on the heterogeneous system equipped with multiple GPUs and achieve high resource utilization. The results show that it can achieve 99 and 90% of theoretical performance for dense general matrix multiplication on one GPU and two GPUs respectively with Nvidia GTX480 or K40 GPUs. It also enables K-means and T-nearest-neighbor algorithms to process larger datasets, which used to be limited by the GPU device memory. We achieve nearly 1.9-fold performance gains by dynamic task scheduling on two GPUs when the performance bottleneck is GPU computing or data transmission.

Toward Dynamic Load Balancing across OpenMP Thread Teams for Irregular Workloads

In the field of high performance computing, massively-parallel many-core processors such as Intel Xeon Phi coprocessors are becoming popular because they can significantly accelerate various applications. In order to efficiently parallelize applications for such many-core processors, several high-level programming models have been proposed. The de facto standard programming model mainly for shared-memory parallel processing is OpenMP. For hierarchical parallel processing, OpenMP version 4.0 or later allows programmers to create multiple thread teams. Each thread team contains a bunch of newly-created synchronizable threads. When multiple thread teams are used to execute an application, it is important to have dynamic load balancing across thread teams, since static load balancing easily encounters load imbalance across teams, and thus degrades performance. In this paper, we first motivate our work by clarifying the benefit of using multiple thread teams to execute an irregular workload on a many-core processor. Then, we demonstrate that dynamic load balancing across those thread teams has a potential of significantly improving the performance of irregular workloads on a many-core processor, with considering the scheduling overhead. Although such a dynamic load balancing mechanism has not been provided by the current OpenMP specification, the benefits of dynamic load balancing across thread teams are discussed through experiments using the Intel Xeon Phi coprocessor. We evaluate the performance gain of dynamic load balancing across thread teams using a ray tracing code. The results show that such a dynamic load balancing mechanism can improve the performance by up to 14% compared to static load balancing across teams, with considering scheduling overhead.

고성능 스토리지를 이용한 Lustre 파일 시스템의 성능 분석 연구

Lustre is a scalable, distributed file system, which is popular in the field of high-performance computing. Recently, the advent of SSD has enabled high-performance storage hardware, but software development requires further improvement. In this paper, we analyzed performance of the Lustre system using SSD via extensive experimentation. We compared performance of Lustre on SSDs and HDDs in terms of file read/write throughputs and metadata access latencies. Our experimental results showed that 1) SSDs improve metadata access performance due to fast random read/write access of SSD characteristics, and 2) SSD are benefited to a greater extent under multiple threads and large numbers of small sized files.

Workshop on high‐performance computational finance

The purpose of this special issue is to collate a selection of representative research articles that were primarily presented at the Seventh Workshop on High-Performance Computational Finance, held in conjunction with SC'14. This annual workshop brings together practitioners, researchers, vendors, and scholars from the complementary fields of computational finance and high-performance computing in order to promote exchange of ideas, discuss future collaborations and develop new research directions. Financial companies increasingly rely on high performance computers to analyze high volumes of financial data, automatically execute trades, and manage risk. As financial market data continue to grow in volume and complexity, computational capabilities of emerging hardware also increases. Extracting high performance from emerging architectures requires a combination of domain knowledge and specialized technical skills. This special issues presents many examples of how researchers, scholars, vendors, and practitioners are collaborating to address high-performance computing research challenges. The scope of this special issue is broad and is representative of the multi-disciplinary nature of computational finance. In addition to submissions that deal with performance and programmability challenges, theoretical analysis, algorithms, and practical experience in computational finance, this issue also includes articles that address practical challenges with running financial applications in the cloud. The efficient deployment of applications on multi and many-core architectures is a central topic in this issue. N. Burke, A. Rau-Chaplin and B. Varghese 1 demonstrate the acceleration of a compute intensive insurance model in their paper. S. Li, and J. Lin 2 describe an implementation of Asian option pricing algorithms on many-core architectures. M. Dixon, M. Zubair, and J. Lötze 3 consider the additional problem of how to preserve portability of compute intensive financial application while simultaneously achieving efficient deployment on the CPU and GPU. This issue would be incomplete without coverage of the highly impactful STAC A2 benchmark, which is designed to measure the performance of market risk analysis workloads. A. Nikolaev, B. Ilya, and S. Sania 4 describe how Intel is actively contributing to the specification and provides updated benchmark implementations optimized for the Intel Xeon processor E5 and E7 product families and Intel Xeon Phi coprocessor. Performance versus accuracy of computational methods is a pervasive topic in the financial modeling. C. Brugger, G. Liu, C. De Schryver, and N. Wehn 5 consider the calibration of various models with closed form solutions and propose a hybrid solution. We encourage the reader to review 6-8 to gain insight into the breadth and depth of problems and innovative solutions in the multi-disciplinary field of high-performance computational finance.

Scaling Support Vector Machines on modern HPC platforms

Support Vector Machines (SVM) have been widely used in data-mining and Big Data applications as modern commercial databases start to attach an increasing importance to the analytic capabilities. In recent years, SVM was adapted to the field of High Performance Computing for power/performance prediction, auto-tuning, and runtime scheduling. However, even at the risk of losing prediction accuracy due to insufficient runtime information, researchers can only afford to apply offline model training to avoid significant runtime training overhead. Advanced multi- and many-core architectures offer massive parallelism with complex memory hierarchies which can make runtime training possible, but form a barrier to efficient parallel SVM design.To address the challenges above, we designed and implemented MIC-SVM, a highly efficient parallel SVM for x86 based multi-core and many-core architectures, such as the Intel Ivy Bridge CPUs and Intel Xeon Phi co-processor (MIC). We propose various novel analysis methods and optimization techniques to fully utilize the multilevel parallelism provided by these architectures and serve as general optimization methods for other machine learning tools.MIC-SVM achieves 4.4–84× and 18–47× speedups against the popular LIBSVM, on MIC and Ivy Bridge CPUs respectively, for several real-world data-mining datasets. Even compared with GPUSVM, running on the NVIDIA k20x GPU, the performance of our MIC-SVM is competitive. We also conduct a cross-platform performance comparison analysis, focusing on Ivy Bridge CPUs, MIC and GPUs, and provide insights on how to select the most suitable advanced architectures for specific algorithms and input data patterns.

A Survey on Parallel Computing and its Applications in Data-Parallel Problems Using GPU Architectures

AbstractParallel computing has become an important subject in the field of computer science and has proven to be critical when researching high performance solutions. The evolution of computer architectures (multi-coreandmany-core) towards a higher number of cores can only confirm that parallelism is the method of choice for speeding up an algorithm. In the last decade, the graphics processing unit, or GPU, has gained an important place in the field of high performance computing (HPC) because of its low cost and massive parallel processing power. Super-computing has become, for the first time, available to anyone at the price of a desktop computer. In this paper, we survey the concept of parallel computing and especially GPU computing. Achieving efficient parallel algorithms for the GPU is not a trivial task, there are several technical restrictions that must be satisfied in order to achieve the expected performance. Some of these limitations are consequences of the underlying architecture of the GPU and the theoretical models behind it. Our goal is to present a set of theoretical and technical concepts that are often required to understand the GPU and itsmassive parallelismmodel. In particular, we show how this new technology can help the field ofcomputational physics,especially when the problem isdata-parallel.We present four examples of computational physics problems;n-body, collision detection, Potts modelandcellular automatasimulations. These examples well represent the kind of problems that are suitable for GPU computing. By understanding the GPU architecture and its massive parallelism programming model, one can overcome many of the technical limitations found along the way, design better GPU-based algorithms for computational physics problems and achieve speedups that can reach up to two orders of magnitude when compared to sequential implementations.

HPC-Cloud在科学研究领域的优势

高性能计算是我国科研领域重要的服务工具，起着不可替代的作用。本文就高性能计算为科学研究领域提供计算服务时遇到的瓶颈问题，提出了初步的解决方案——高性能计算云平台，总结了高性能计算云平台的国内外现状。针对科学研究领域应用的特点设计了HPC-Cloud系统的主要功能，并以典型案例表明高性能计算云平台在解决计算密集型应用问题上的优势。 High-performance computing is an important service aid and plays an irreplaceable role in the field of scientific research in China. In this dissertation, it proposes a preliminary solution——high-performance computing cloud platform, for the bottleneck problem in the field of high-performance computing when providing computing service, and summarizes the present situation of high-performance computing cloud platform at home and abroad. Main functions of HPC-Cloud system are designed according to the characteristics that apply in the field of scientific research. It also shows the advantages of high-performance computing cloud platform according to a typical case in solving problems of intensive computing applications.

Preface to high performance computing applied to computational problems in science and engineering

As a part of the 11th International Conference on “Computational and Mathematical Methods in Science and Engineering” (CMMSE 2011), the Minisymposium “High Performance Computing (HPC) applied to Computational Problems in Science and Engineering” took place in Benidorm on 26 and 27 of June. It brought together over 100 researchers associated within the field of HPC, who participated in the various oral and poster sessions. In last years, the number of scientific contributions and research projects related to the HPC based on the use of parallel computers (multicore processors, Graphics Processing Units—GPU—or clusters of computers) has significantly increased. This phenomenon has occurred in almost all engineering fields that require intensive computing. Heterogeneous parallel computers based on manycore (GPU) and multicore microprocessors are fascinating tools and represent a quantitative leap in the development of high performance hardware. Probably it would be impossible to go back,

Optimization of Shared High-Performance Reconfigurable Computing Resources

In the field of high-performance computing, systems harboring reconfigurable devices, such as field-programmable gate arrays (FPGAs), are gaining more widespread interest. Such systems range from supercomputers with tightly coupled reconfigurable hardware to clusters with reconfigurable devices at each node. The use of these architectures for scientific computing provides an alternative for computationally demanding problems and has advantages in metrics, such as operating cost/performance and power/performance. However, performance optimization of these systems can be challenging even with knowledge of the system’s characteristics. Our analytic performance model includes parameters representing the reconfigurable hardware, application load imbalance across the nodes, background user load, basic message-passing communication, and processor heterogeneity. In this article, we provide an overview of the analytical model and demonstrate its application for optimization and scheduling of high-performance reconfigurable computing (HPRC) resources. We examine cost functions for minimum runtime and other optimization problems commonly found in shared computing resources. Finally, we discuss additional scheduling issues and other potential applications of the model.

Accelerating an Imaging Spectroscopy Algorithm for Submerged Marine Environments Using Graphics Processing Units

Remote sensing is utilized across a wide array of disciplines, including resource management, disaster relief planning, environmental assessment, and climate change impact analysis. The data volume and processing requirements associated with remote sensing are rapidly expanding as a result of the increasing number of satellite and airborne sensors, greater data accessibility, and expanded utilization of data intensive technologies such as imaging spectroscopy. However, due to the limited ability of current computing systems to gracefully scale with application requirements, particularly in the desktop level market, large amounts of data are currently underutilized or never explored. Computing limitations thus constrain our ability to efficiently and accurately address key science questions using remote sensing. The current evolution in general purpose computing on Graphics Processing Units (GPUs), an emerging technology that is redefining the field of high performance computing, facilitates significantly improved computing capabilities for current and future image analysis needs. We demonstrate the advantages of this technology by accelerating an imaging spectroscopy algorithm for submerged marine habitats using GPU computing. Results indicate that considerable improvement in performance can be achieved using a single GPU on a standard desktop computer. This technology has enormous potential for continued growth exploiting high performance computing, and provides the foundation for significantly enhanced remote sensing capabilities.

MPtostream: an OpenMP compiler for CPU-GPU heterogeneous parallel systems

In light of GPUs’ powerful floating-point operation capacity, heterogeneous parallel systems incorporating general purpose CPUs and GPUs have become a highlight in the research field of high performance computing(HPC). However, due to the complexity of programming on GPUs, porting a large number of existing scientific computing applications to the heterogeneous parallel systems remains a big challenge. The OpenMP programming interface is widely adopted on multi-core CPUs in the field of scientific computing. To effectively inherit existing OpenMP applications and reduce the transplant cost, we extend OpenMP with a group of compiler directives, which explicitly divide tasks among the CPU and the GPU, and map time-consuming computing fragments to run on the GPU, thus dramatically simplifying the transplantation. We have designed and implemented MPtoStream, a compiler of the extended OpenMP for AMD’s stream processing GPUs. Our experimental results show that programming with the extended directives deviates from programming with OpenMP by less than 11% modification and achieves significant speedup ranging from 3.1 to 17.3 on a heterogeneous system, incorporating an Intel Xeon E5405 CPU and an AMD FireStream 9250 GPU, over the execution on the Xeon CPU alone.

Research and Application of Parallel Computing Technologies based on CUDA and OpenCL

The increased computational performance in science and engineering has led to the strong need for arithmetic intensive parallel computing, CUDA (Compute Unified Device Architecture) and OpenCL (Open Computing Language) are parallel computing technologies proposed in recent years, which both have a great expanse of application prospect in the field of high performance computing. In this paper, we discuss the parallel computing technologies based on CUDA and OpenCL by applying them on the smoking simulation based on real-time physics. Real-time physics requires high real-time quality and authenticity. We build the 3D smoking simulation model using the Computational Fluid Dynamics method and render the smoke using 3D texture volume rendering method to represent the 3D smoking simulation veridical and accurately. In order to ensure the real-time quality of 3D smoking simulation, we respectively adopt CUDA and OpenCL parallel computing technologies applied on different hardware platforms, achieving the solving of 3D smoking simulation in parallel. Experimental results show that compared with CPU serial programming, CUDA and OpenCL parallel computing technologies have predominant operability and inevitable efficiency advantages on arithmetic intensive parallel computing.

TH-1: China’s first petaflop supercomputer

In recent years, heterogeneous systems and cooperative computing have become popular research directions in the field of high performance computing. With fast scaling of the size of high performance computer systems, problems such as power consumption and reliability come to the forefront. The aim of high performance computing has thus shifted from merely seeking peak performance to comprehensively pursuing high efficiency, which takes into consideration many factors including performance, cost, power, reliability and so on. A heterogeneous computing system consisting of general-purpose CPU(s) and special-purpose accelerator(s) features high performance, lower power consumption and low cost, etc. Hence, it has already become the mainstream in the field of high performance computing. However, such systems still face many challenges and problems, for example, programmability and reliability. In this paper, we firstly analyze the main challenges facing heterogeneous computing systems. Then, we introduce the architecture of the first petaflop computing system in China, the Tianhe-1 (TH-1) heterogeneous system, including its hardware/software interface and interconnect network. During development of the TH-1 system, several challenges were encountered; research into the solutions of these challenges is subsequently presented.

From Silicon to Science

The field of high performance computing (HPC) currently abounds with excitement about the potential of a broad class of things called accelerators . And, yet, few accelerator based systems are being deployed in general purpose HPC environments. Why is that? This article explores the challenges that accelerators face in the HPC world, with a specific focus on FPGA based systems. We begin with an overview of the characteristics and challenges of typical HPC systems and applications and discuss why FPGAs have the potential to have a significant impact. The bulk of the article is focused on twelve specific areas where FPGA researchers can make contributions to hasten the adoption of FPGAs in HPC environments.