Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

Zhe Wang,Biao Guo,Ling Wang,Ji-Bo Wei,Qi Tang

doi:10.3390/electronics9091461

Zhe Wang, Biao Guo + Show 3 more

Open Access

https://doi.org/10.3390/electronics9091461

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Abstract

Dynamically partially reconfigurable (DPR) technology based on FPGA is applied extensively in the field of high-performance computing (HPC) because of its advantages in processing efficiency and power consumption. To make full use of the advantages of DPR in execution efficiency, we build a DPR system model that meets to the actual application requirements and the objective constraints. According to the consistency of reconfiguration order and dependencies, we propose two algorithms based on simulated annealing (SA). The algorithms partition FPGA resource to several regions and schedule tasks to the regions. In order to improve the performance of the algorithms, we exploit the module merging technology to improve the parallelism of task execution and design a new solution generation method to speed up the convergence speed. Experimental results show that the proposed algorithms have a lower time complexity than mixed-integer linear programming (MILP), iterative scheduler (IS) and Ant Colony Optimization (ACO). For applications with more tasks, the proposed algorithms show performance advantages in producing better partitioning and scheduling results in a shorter time.

Highlights

In the last few years, it is hard for the performance of CPU to get a bigger boost with IC transistor integration density approaching threshold value
We jointly solve the problem of resource partitioning and application scheduling and consider many physical constraints; We introduce module merging technology to improve execution efficiency; We propose two algorithms based on simulated annealing which can be utilized to solve a optimal solution in a short time; The effectiveness of our proposed algorithms are evaluated on a number of benchmarks abstracted by piratical applications and compared with three approaches
This paper proposes a partitioning and scheduling model for Dynamically partially reconfigurable (DPR) system, and designs a solution method based on simulated annealing algorithm to solve the model

Summary

Introduction

In the last few years, it is hard for the performance of CPU to get a bigger boost with IC transistor integration density approaching threshold value. Due to dynamic time-multiplexing, finite space resources can be extended indefinitely in the time domain, which enables the reconfigurable system to execute applications with greater resource requirements on the chip system of finite resources This technology can divide FPGA resources into multiple logic regions, so that the execution process between different regions does not Electronics 2020, 9, 1461; doi:10.3390/electronics9091461 www.mdpi.com/journal/electronics. We jointly solve the problem of resource partitioning and application scheduling and consider many physical constraints; We introduce module merging technology to improve execution efficiency; We propose two algorithms based on simulated annealing which can be utilized to solve a optimal solution in a short time; The effectiveness of our proposed algorithms are evaluated on a number of benchmarks abstracted by piratical applications and compared with three approaches.

Related Work

Problem Formulation

Platform Model

Application Model

The Partitioning and Scheduling Problem

Insight of the Studied Problem

Module Merging

The Reconfiguration-Dependency Non-Consistent Algorithm Based on Simulated

Structure of the Simulated Annealing Algorithm

Solution Structure

Disturbance Method with Module Merging

Solution Feasibility Evaluation