Gate Oxide Field Research Articles

Evidence on p -MOSFET recovery characteristics under NBT stress

An investigation on the recovery characteristics of p-MOSFET with ultra-thin decoupled plasma nitrided gate oxide under negative bias temperature (NBT) stress is presented. The electron trapping assisted NBTI recovery mechanism is proposed with new evidence on the dependence of recovery rate on source/drain voltage, i.e. gate oxide field. Further, the findings about the different gate current behaviour and the source/drain voltage dependency indicate that the relaxation of positive charge, instead of interface trap, is the major component in the NBTI recovery stage.

Lateral 4H-SiC MOSFETs with Low On-Resistance by Using Two-Zone Double RESURF Structure

4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

1500V SiC DIMOSFET Development

In the process of developing high voltage (1500V) SiC power DIMOSFETs, both channel mobility and gate reliability were investigated. Using a MOS-gated Hall structure, the sheet carrier concentration and electron mobility were measured versus gate bias at various temperatures. The Hall mobility increases with increasing temperature, indicating that Coulombic scattering limits the inversion-layer mobility in these SiC MOSFETs at these fields. The gate oxide reliability of thermally-grown oxides on SiC has been characterized by time-dependent dielectric breakdown (TDDB) measurements of MOS capacitors, lateral MOSFETs, and vertical DIMOSFETs fabricated on 4H-SiC. Simple MOS CV dots demonstrate the potential for >10^6 hours lifetime for a gate oxide field < 4MV/cm. However, fully processed lateral or vertical MOSFET devices demonstrated distinctly lower predicted lifetimes and even different failure modes.

Radiation-induced breakdown in 1.7 nm oxynitrided gate oxides

We present new experimental data about the radiation-induced breakdown in 1.7 nm gate oxides, typical of the 90nm technology node. We irradiated several MOS capacitors with n- and p-type substrates and different areas under a positive and negative staircase bias with Ag ions. A modified testing procedure was introduced based on a low voltage sensing of the gate current during irradiation. We showed that, even in spite of a smaller gate oxide field, irradiation was more damaging for biases in deep depletion than for biases in accumulation. We attributed this to the injection in the oxide of energetic carriers heated in the depletion region. In this regime of operation, we highlighted the differences in the gate current degradation of nMOS and pMOS devices: abrupt changes followed by a smooth growth in the first ones, an increase proportional to the area in the second.

Ultrathin oxide reliability after combined constant voltage stress and substrate hot electron injection

An experimental investigation on ultra-thin oxides under combined substrate hot-electron injection (SHEI) and tunnelling electrical stress (CVS) is reported. We study the electrical properties of 2.5–1.5 nm-thick SiO 2 oxides in N-channel metal–oxide–semiconductor (NMOS) field effect transistors. CVS stress at V G = +3.5 V does not affect the transistor operating parameters but does increase, up to a factor of 10, the gate current. We have verified that the critical parameter of CVS stress is the gate voltage bias, consequently we suggest a model based on energetic electrons creating damage, which, correctly describes the reliability of ultra-thin SiO 2 at CVS condition. In comparison SHEI is observed to be not only dependent on gate bias but also on the electric field in the oxide. A comparison of each parameter either injected charge or current, gate and substrate voltage or oxide field is experimentally done. Based on these and previous results, the defect creation probability for CVS and SHEI stress is fitted over gate voltage to resolve two defect generation mechanisms.

Dose Designing for High-Voltage 4H-SiC RESURF MOSFETs - Device Simulation and Fabrication

Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.

Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs

Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.

Damage generation and location in n- and p-MOSFETs biased in the Substrate-Enhanced Gate Current regime

This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel.

A study of interface trap generation by Fowler-Nordheim and substrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO/sub 2/ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D/sub it/) generation due to hot holes under V/sub G/<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D/sub it/) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D/sub it/) than SHH stress. It is also observed that N/sub 2/O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O/sub 2/-grown oxide. N/sub 2/O-grown gate oxide is shown to have less SHH stress-induced interface traps than O/sub 2/-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices.

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 /spl mu/m drift region), a specific on-resistance of 15.7 m/spl Omega/-cm/sup 2/ at room temperature, and a gate oxide field of 3 MV/cm.

Radiation‐Induced Neutral Electron Trap Generation in Electrically Biased Insulated Gate Field Effect Transistor Gate Insulators

Optically assisted electron injection was employed to quantify neutral electron trap and fixed positive charge concentrations in the gate oxides of electrically biased n‐channel insulated gate field effect transistors exposed to 10 keV x‐rays. This is the first known work to study the effects of an applied gate oxide field during x‐ray irradiation on neutral electron trap generation. Surprisingly, the results show that neutral electron trap generation is dependent upon the gate bias, and the oxide thickness in a similar manner as positive charge buildup during irradiation. This possibly suggests an association between the two defect types. A neutral electron trap generation model is proposed in which the trapped hole center transforms into a dipolar neutral electron trapping site via electron compensation by an electron.

Gate-oxide breakdown accelerated by large drain current in n-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 mu m, gate width-15 mu m) occurs in approximately 100 s at an applied gate oxide field of approximately 5.2 MV/cm during the high drain current stress, while it occurs in approximately 100 s at an applied gate oxide field of approximately 10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method. >

A modification to the Fowler-Nordheim tunneling current calculation for thin MOS structures

This paper presents a new computer modeling of Fowler-Nordheim (F-N) tunneling current from an inverted silicon surface to the metal gate of the thin oxide MOS structures. In this model the tunneling current through the oxide is taken to be proportional to the product of the gate oxide field and the inversion layer carrier concentration. Within the semiconductor the standard semiconductor equations are solved to ensure electron current at the semiconductor surface is equal to the tunneling current through the oxide. The computational results indicate that the current-voltage characteristics of the structure would saturate if it is limited by carrier generation in the space-charge region of the silicon. This is known from previous experimental results reported in the literature.

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.

CMOS Scaling Implications for Total Dose Radiation

Scaling of CMOS device channel lengths can result in increased threshold voltage shifts after exposure to total dose radiation. An analytical model has been developed in order to predict these threshold voltage changes as a function of gate length and total dose for both gate oxide and parasitic thick field oxide transistors. Measurements show large increases in threshold voltage shifts after irradiation as gate lengths are decreased. The model is proven accurate to a total dose level of 106 rads (SiO2) and gate lengths down to 0.9 um. Scaling of field oxide gate lengths can have a severe impact on total dose hardness.

Experimental derivation of the source and drain resistance of MOS transistors

A new method for experimentally deriving the source-and-drain resistance of MOS transistors is presented along with experimental results verifying its accuracy. The method also yields the mobility reduction with high gate-oxide field. The measurements are done on two (or more) MOS transistors which are identical except that their gate lengths differ by a known amount.