Field Effect Transistor Technology Research Articles

Power Gallium Nitride Technology: The Need for Efficient Power Conversion

The biggest motivation and driver for semiconductor power device innovation is improved efficiency in power conversion. Power gallium nitride (GaN) technology shows the greatest performance benefits against other incumbent technologies, including silicon (Si) technology. A reduction in power losses is the key challenge industries are facing. Pressure from society and government legislation for reduced CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> emission are all trending toward more efficient power conversion and electrification. Automotive electrification, telecom infrastructure, server storage, and industrial automation using power electronics are the biggest trends in the technology sector. GaN field-effect transistors (FETs) can enable us to achieve the best efficiency with lower system costs while making systems lighter, smaller, and cooler. Electrification in the automotive sector can be the biggest beneficiary of this new power GaN FET technology.

Epitaxial growth of a silicon capping layer to mitigate roughness after the selective chemical etching of Si1-xGex

The gate-all-around structure is a promising candidate for future generations of advanced metal-oxide semiconductor field-effect transistor technologies, as it provides higher drive current and low-power operation. The commonly-suggested nanowire structure uses a selective etching technique in the silicon/silicon-germanium multilayer to reveal the channel area. The revealed Si surface is rough, however, due to the missing atoms and remnants of Si1-xGex. This leads to increased interfacial state density, which degrades device performance, such as subthreshold voltage swing. Regarding the usage of high-k metal gates on the channel area, the issue of this rough surface, and the subsequent increase of the dangling bonds after etching, should be properly addressed.In this study, we report the enhanced roughness and density of interface state by applying a Si capping layer. The epitaxial Si0.87Ge0.13 layer, with a thickness of 30 nm on the Si substrate, was removed by an etchant consisting of nitric acid, hydrofluoric acid, and acetic acid, after which a 1-nm thick Si capping layer was epitaxially grown onto the surface. Atomic Force Microscopy was used to measure the roughness, and X-ray Photoelectron Spectroscopy was conducted to characterize the atomic bonds on the surface. A 10-nm thick SiO2 film was deposited using the Atomic Layer Deposition process to characterize the capacitance-voltage curve and interface trap density. The Si-capped sample exhibited half of the surface roughness of the un-capped sample, and exhibited a 30% lower interface trap density, by mitigating the impact of wet etching.

Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies

The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.

Solid-State FET-Based Sensors Capable of Measuring Acidity of Lubricants

Introduction The deterioration of various kinds of machine lubricants and engine oils has been estimated through total acid number (TAN), and the value of TAN has been commonly measured by color-indicator titration and potentiometric titration, according to ISO standards (e.g., No. 6619 and 7537). Presently, we cannot directly monitor the TAN value on site as well as in real time, which leads the difficulty in the efficient operation of various machines and their automatic maintenance. Some kinds of devices capable of measuring nuclear magnetic resonance (NMR) [1], infrared (IR) adsorption [2], impedance [3], or electrochemical potential [3–6] of lubricants and oils to estimate their deterioration have been developed, but compact, maintenance-free, and low-cost devices capable of directly monitoring their TAN values are quite convenient for controlling mechanical systems utilized in various fields. Our group have recently attempted to develop new TAN-monitoring sensors employing a general pH meter based on ion-sensitive field-effect transistor (IS-FET) technology [7–9]. In this presentation, we would like to introduce the new concept, fundamental properties, and the operating mechanism of the sensors. Experimental Figure 1 shows schematic cross-sectional drawing of a sensor tip, which consists of an IS-FET and a reference electrode (Horiba, Ltd., ISFET pH electrode: 0040-10D, sensor chip: 0141) [10]. 1-Propanol solution containing 5.0 wt% cation-conducting polymer (Tokuyama Corp., CS-7P) was used as an original coating agent, and it was appropriately diluted with 1-propanol to form three kinds of diluted CCP solution (2.5 wt%, 1.7 wt%, and 1.3 wt%). The CCP solution (20 mm3) was dropped on the surface of the sensor tip, and then the CCP film was uniformly coated on the while surface containing the IS-FET and the reference electrode, after moderately drying at room temperature. The obtained films were expressed as CCP(m), where m stands for the concentration of the CCP solution used (wt%). Subsequently, the surface of the sensor tip was treated with 1 M NaCl aqueous solution (100 mm3) several times in order to exchange H+ for Na+ in the CCP(m) films, until the pH value reached up to ca. 6. As soon as some kinds of lubricants (20 mm3) were dropped on the surface of the obtained CCP(m) sensors, variations in pH of the lubricants measured by the CCP(m) sensors with time were measured with a pH meter (Horiba, Ltd., D-52). Results and Discussion Figure 2 shows response transients of the CCP(2.5) sensor to typical fresh and deteriorated lubricants (Oil(n), n: oxidation period for deterioration (h)) at 30°C. TAN values of the lubricants oxidized for 0, 504, 800, and 1104 h were 0.19, 0.23, 0.30, and 0.35 (mgKOH/g), respectively, and the fresh lubricant corresponds to Oil(0). After the initial pH value was controlled at ca. 6, the pH value gradually increased immediately after dropping the Oil(0) on the sensor surface (i.e., starting the pH measurement of the lubricant), and it reached a constant value of ca. 7.5. On the other hand, the pH value decreased soon after dropping other oxidized Oil(n)s on the sensor surface, and the pH value decreased with an increase in the oxidation period. Consequently, the pH value of all the Oil(n)s was largely dependent on the oxidation period and the TAN value. In addition, the response speed of the CCP(2.5) sensor to all the Oil(n)s was much faster than the deterioration rate of general lubricants under common usage conditions. These results show that the sensor is really promising as a device monitoring the deterioration of various lubricants on site as well as in real time. We will report effects of thickness of the CCP film on the response behavior and response transients of CCP(m) sensors to other kinds of lubricants and discuss their operating mechanism in this presentation.

Subthermionic negative capacitance ion sensitive field-effect transistor

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for the gate and the definition of fully depleted and gate all around structures. Negative Capacitance (NC) is an emerging concept exploiting ferroelectric materials integrated in field effect transistor gate stacks in order to decrease their subthreshold swing and improve the drain current (ID) overdrive in order to reach more energy efficient devices, operated at lower voltage. In this work, we investigate and experimentally demonstrate the application of this concept to enable subthermionic ISFETs with enhanced current sensitivity and low power operation. A physical model for the introduced NC ISFET is presented and optimized by fitting of the experimental results, providing further insights into the sensor parameters and a predictive tool for the design of future NC-based sensors.

SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology

A new technique called series-connected dynamic node-driven transistor domino logic (SCDNDTDL) is proposed for the design of circuits with high speed and low power consumption in fin-shaped field-effect transistor (FinFET) technology. HSPICE is used to simulate 2-, 4-, 8-, and 16-input domino OR gates in complementary metal–oxide–semiconductor (CMOS) and FinFET technology using the 32-nm Predictive Technology Model (PTM) library with a supply voltage of 0.9 V. The proposed technique shows a maximum power reduction of 73.16% in the FinFET short gate (SG) mode as compared with the conditional stacked keeper domino logic (CSK-DL) technique and a maximum delay reduction of 36.36% in the FinFET SG mode as compared with the voltage comparison-based domino (VCD) technique at a frequency of 50 MHz. The unity noise gain of the proposed circuit is 1.64 to 3.77 times higher in the FinFET SG mode and 1.39 to 3.77 times higher in the FinFET low-power (LP) mode compared with different existing techniques. The proposed circuit has up to 18.94 times higher figure of merit (FOM) in the SG mode and up to 7.14 times higher FOM in the LP mode compared with existing techniques. The proposed circuit in FinFET technology shows a maximum power reduction of 68.47% as compared with its counterpart in CMOS technology for a 16-input OR gate. The proposed circuit has 6.06 times lower energy–delay product and 4.53 times lower power–delay product compared with its counterpart in CMOS technology for a 16-input OR gate.

An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate.

Impact of strained channel on electrical properties of Junctionless Double Gate MOSFET

Application of strained channel in Metal-oxide-semiconductor Field Effect Transistors (MOSFET) technology influences the electrical properties due to the significant changes in the energy band structure of silicon lattices. Thus, in this paper, a comprehensive analysis is conducted to investigate the impact of strained channel towards several electrical properties of junctionless double-gate MOSFET. The comparative analysis is carried out by simulating two different sets of device structure which are JLDGM device (without strain) and junctionless double-gate strained MOSFET (JLDGSM) device. The results show that the strained channel has improved the on-state current (ION), on-off ratio, transconductance (gm) and transconductance generation factor (TGF) by approximately 58 %, 98%, 98%, and 44% respectively. The significant improvement is mainly attributed to the presence of biaxial strain boosting the electron mobility in the channel. The intrinsic gate delay (τint) has significantly reduced by approximately 52% as the strained channel is applied. Since the variation of intrinsic gate capacitances (Cint) is very minimal (4%) as the strained channel is applied, the gate delay is dominantly governed by the drain current. However, the application of strain channel has increased the dynamic power dissipation (Pdyn) for approximately 19% mainly due to slightly increased intrinsic gate capacitances.

Research progress in Ge-based advanced field effect transistor technology

The modern integrated circuit is among the world's mostcomplex systems, but at its heart is a very simple, and we think beautiful,device: the transistor. Right now, 7 nm process technology is the cutting edge in traditional silicon-based integrated-circuit-manufacturing industry. However,the downscaling of the technological node in accordance with Moore's Law is becomingincreasingly difficult, not to mention fantastically expensive. Ge has beenconsidered a promising channel material due its high hole andelectron motilities, which facilitate the drive-current boost withoutdownscaling the device's dimensions. This paper summaries the current state-of-the-art Gemetal-oxide-semiconductor field-effect transistors (MOSFETs) from these three angles: gate stacks, source/drainformation, and new device structure. It is found that many criticalphysical and engineering problems concerning Ge MOSFETs are still under discussion, including basic device fabrication and the deep physicalunderstanding of Ge MOSFETs. Nevertheless, Ge MOSFETs reported by bothacademic and industrial researchers show superior performance totraditional Si MOSFETs, suggesting that Ge is a promising material for future high-performance complementary-MOS (CMOS) devices under 3 nm node.

Crossover-aware Placement and Routing for Inkjet Printed Circuits

Printed Electronics technology is a key-enabler for smart sensors, soft robotics, and wearables. The inkjet printed electrolyte-gated field effect transistor (EGFET) technology is a promising candidate for such applications due to its low-power operation, high field-effect mobility, and on-demand fabrication. Unlike conventional silicon-based technologies, inkjet printed electronics technology is an additive manufacturing process where multiple layers are printed on top of each other to realize functional devices such as transistors and their interconnections. Due to the additive manufacturing process, the technology has limited routing layers. For routing of complex circuits, insulating crossovers are printed at the intersection of routing paths to isolate them. The crossover can alter the electrical properties of a circuit based on specific location on a routing path. In this work, we propose a crossover-aware placement and routing (COPnR) methodology for inkjet-printed circuits by integrating the crossover constraints in our design framework. Our proposed placement methodology is based on a state-of-the-art evolutionary algorithm while the routing optimization is done using a genetic algorithm. The proposed methodology is compared with the industrial standard placement and routing (PnR) tools. On average, the proposed methodology has 38% fewer crossovers and 94% fewer failing paths compared to the industrial PnR tools applied to printed circuit designs.

A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology

In this paper a ternary half adder is proposed and designed using carbon nano-tube field effect (CNFET) transistors. This novel design in ternary logic is based on multiplexers and level converters. The performance of the proposed design is examined against different supply voltages and a range of temperatures and fan-outs. Propagation delay time, power consumption, power-delay product (PDP) and transistor count are compared between the proposed ternary half adder and prior works. It is shown that the delay time in the proposed design can be improved by 75% with respect to other works while the PDP can be improved at least by 5%. Moreover, the transistor count in the novel design is less than other works at least by 10%. Therefore, it can be a promising candidate for the design of next generation of adder circuits in digital logic systems and ALU blocks.

C$^\text{2}$TIG: Dynamic C$^\text{2}$MOS Design Based on Three-Independent-Gate Field-Effect Transistors

Dynamic logic has become a niche approach in circuit design, mainly due to the reliability limitations that have been aggravated with process down-scaling. To that extent, the performance and area benefits of dynamic design approaches, such as the integration of the Clocked CMOS (C $^{2}$ MOS) approach, are left on the table. In this article, we propose employing the Three-Independent-Gate Field-Effect Transistor (TIGFET) technology for the implementation of the C $^\text{2}$ MOS approach, which we call the Clocked Complementary TIG (C $^\text{2}$ TIG) approach. Electrical simulations at 22nm demonstrate the enhanced robustness of the C $^\text{2}$ TIG approach, while providing gains in power, performance, and area. Finally, new design opportunities for synchronous systems are demonstrated with the C $^\text{2}$ TIG approach.

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits.

Dimer-vacancy defects on Si(1 0 0): The role of nickel impurity

Using scanning tunneling microscopy, x-ray photoelectron spectroscopy, and low-energy electron diffraction, we have studied clean and Ni-containing Si(1 0 0) surfaces and shown that the Ni contamination can easily appear at the Si(1 0 0) during its annealing at high temperature (1230 °C) because of migration of this impurity from heated parts of the sample holder, even though they are nominally Ni-free. The difference of dimer-vacancy (DV) defects, which are common features of Si(1 0 0), and their patterns on both surfaces is examined. It is also found that the density of DV defects on the Ni-contaminated surface is proportional to the number of Ni atoms. The analysis indicates that the fully saturated DV structure, i.e., Ni-induced Si(1 0 0)(2 × n) phase contains one metal atom per defect. The findings are valuable for constructing atomic models of defects on the Si(1 0 0) as well as preparation of clean Si(1 0 0) substrate and monitoring the Ni segregation on its surface. In addition, the results can be useful for Ni silicide metal-contact formation in metal-oxide-semiconductor field-effect transistor technology.”

A review on nanomaterial-based field effect transistor technology for biomarker detection.

Field effect transistor (FET) based sensors have attractive features such as small size, ease of mass production, high versatility and comparably low costs. Over the last decade, many FET type biosensors based on various nanomaterials (e.g. silicon nanowires, graphene, and transition metal dichalcogenides) have been developed to detect various classes of biomolecular targets due to their integration into portable and rapid test systems, both for use in the clinical lab and in point-of-care testing. This review (with 197 refs.)starts with an introduction into the specific features of FET biosensor technology. This is followed by a description of the essentials of methods for immobilization of recognition elements. The next section discusses the progress that has been made in FET based biosensors using semiconducting nanostructures composed of silicon, graphene, metal oxides, and transition metal dichalcogenides. A further section is devoted to microfluidic systems combined with FET biosensors. We then emphasize the biosensing applications of these diagnostic devices for analysis of clinically relevant biomarkers, specifically to sensing of neurotransmitters, metabolites, nucleic acids, proteins, cancer and cardiac biomarkers. Two tables are presented which summarize advances in applications of 1D and 2D nanomaterial-based FETs for biomarker sensing. A concluding section summarizes the current status, addresses current challenges, and gives perspective trends for the field. Graphical abstract Field effect transistor devices based on the use of1D and 2D semiconductor nanostructures (so called nano-FETs) are making use of materials including silicon nanowires, graphene, zinc oxide, indium oxide, titanium oxide, and molybdenum disulfidethat are further modified with recognition elements for biosensing application.

Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function

A physical unclonable function (PUF) is a hardware circuit that produces a random sequence based on its manufacturing-induced intrinsic characteristics. In the past decade, silicon-based PUFs have been extensively studied as a security primitive for identification and authentication. The emerging field of printed electronics (PE) enables novel application fields in the scope of the Internet of Things (IoT) and smart sensors. In this paper, we design and evaluate a printed differential circuit PUF (DiffC-PUF). The simulation data are verified by Monte Carlo analysis. Our design is highly scalable while consisting of a low number of printed transistors. Furthermore, we investigate the best operating point by varying the PUF challenge configuration and analyzing the PUF security metrics in order to achieve high robustness. At the best operating point, the results show areliability of 98.37% and a uniqueness of 50.02%, respectively. This analysis also provides useful and comprehensive insights into the design of hybrid or fully printed PUF circuits. In addition, the proposed printed DiffC-PUF core has been fabricated with electrolyte-gated field-effect transistor technology to verify our design in hardware.

Design 10-Transistor (10t) Sram using Finfet Technology

This paper discuss designing of low power, high-speed 10-Transistor (10T) SRAM and analysis of SRAM cell in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and FinFET technology. MOSFET is used widely in many areas, but below 40 nm technology control of channel region becomes extremely difficult. So there is a necessity for new innovative technology which allows designers to design below 40nm technology and can offer excellent control over gate thus reducing short channel effects. The designing of SRAM is analyzed using TANNER EDA tool and Microwind.

Photonic crystal for graphene plasmons

Photonic crystals are commonly implemented in media with periodically varying optical properties. Photonic crystals enable exquisite control of light propagation in integrated optical circuits, and also emulate advanced physical concepts. However, common photonic crystals are unfit for in-operando on/off controls. We overcome this limitation and demonstrate a broadly tunable two-dimensional photonic crystal for surface plasmon polaritons. Our platform consists of a continuous graphene monolayer integrated in a back-gated platform with nano-structured gate insulators. Infrared nano-imaging reveals the formation of a photonic bandgap and strong modulation of the local plasmonic density of states that can be turned on/off or gradually tuned by the applied gate voltage. We also implement an artificial domain wall which supports highly confined one-dimensional plasmonic modes. Our electrostatically-tunable photonic crystals are derived from standard metal oxide semiconductor field effect transistor technology and pave a way for practical on-chip light manipulation.

Three-dimensional imaging of integrated circuits with macro- to nanoscale zoom

The imaging of integrated circuits across different length scales is required for failure analysis, design validation and quality control. At present, such inspection is accomplished using a hierarchy of different probes, from optical microscopy on the millimetre length scale to electron microscopy on the nanometre scale. Here we show that ptychographic X-ray laminography can provide non-destructive, three-dimensional views of integrated circuits, yielding both images of an entire chip volume and high-resolution images of arbitrarily chosen subregions. We demonstrate the approach using chips produced with 16 nm fin field-effect transistor technology, achieving a reconstruction resolution of 18.9 nm, and compare our results with photolithographic mask layout files and more conventional imaging approaches such as scanning electron microscopy. The technique should also be applicable to other branches of science and engineering where three-dimensional X-ray images of planar samples are required. A technique that combines X-ray ptychography with laminography can provide three-dimensional views of integrated circuits, yielding both images of entire chip volumes and high-resolution images of arbitrarily chosen subregions, and is applicable to any imaging problem where the samples are planar.

A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology

ABSTRACTThis paper proposes a 4:1 Multiplexer (MUX) designed using proposed Dual Chirality High-Speed Noise Immune Domino Logic (DCHSNIDL) technique for designing lower delay noise immune domino logic circuits in Carbon Nanotube Field Effect Transistors (CNTFETs) technology. Dynamic power consumption, speed and noise immunity of the circuit are improved by changing the threshold voltage of the CNTFETs. The chirality indices of the carbon nanotubes (CNTs) are varied to change the threshold voltage of the CNTFETs. Simulations are carried out for 32 nm Stanford CNTFET model in HSPICE for 2-, 4-, 8- and 16-input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9V. The proposed DCHSNIDL domino circuit reduces power consumption by a maximum of 61.77% and propagation delay by a maximum of 55.11% compared to Current-Mirror Based Process Variation Tolerant (CPVT) circuit in CNTFET technology. The proposed CNTFET-based domino technique shows a maximum reduction of 96.31% in power consumption compared to its equivalent circuit in CMOS technology for a 4-input OR gate. The proposed technique shows an improvement of 1.04× to 1.35× times in Unity Noise Gain (UNG) compared to various existing techniques in CNTFET technology. The 4:1 MUX designed using proposed technique has 48.91% lower propagation delay and consumes 52.80% lower power compared to MUX using CPVT technique.