C$^\text{2}$TIG: Dynamic C$^\text{2}$MOS Design Based on Three-Independent-Gate Field-Effect Transistors

Abstract

Dynamic logic has become a niche approach in circuit design, mainly due to the reliability limitations that have been aggravated with process down-scaling. To that extent, the performance and area benefits of dynamic design approaches, such as the integration of the Clocked CMOS (C $^{2}$ MOS) approach, are left on the table. In this article, we propose employing the Three-Independent-Gate Field-Effect Transistor (TIGFET) technology for the implementation of the C $^\text{2}$ MOS approach, which we call the Clocked Complementary TIG (C $^\text{2}$ TIG) approach. Electrical simulations at 22nm demonstrate the enhanced robustness of the C $^\text{2}$ TIG approach, while providing gains in power, performance, and area. Finally, new design opportunities for synchronous systems are demonstrated with the C $^\text{2}$ TIG approach.