Field Effect Transistor Technology Research Articles

Monitoring of Ammonium and Nitrate Ions in Soil Using Ion-Sensitive Potentiometric Microsensors.

Focusing on the ChemFET (chemical field-effect transistor) technology, the development of a multi-microsensor platform for soil analysis is described in this work. Thus, different FET-based microdevices (i.e., pH-ChemFET pNH4-ISFET and pNO3-ISFET sensors) were realized with the aim of monitoring nitrogen-based ionic species in soil, evidencing quasi-Nernstian detection properties (>50 mV/decade) in appropriate concentration ranges for agricultural applications. Using a specific test bench adapted to important earth samples (mass: ~50 kg), first experiments were done in a lab, mimicking rainy periods as well as nitrogen-based fertilizer inputs. By monitoring pH, pNH4, and pNO3 in an acidic (pH ≈ 4.7) clay-silt soil matrix, different processes associated to the nitrogen cycle were characterized over a fortnight, demonstrating comprehensive results for ammonium nitrate NH4NO3 inputs at different concentrations, water additions, nitrification phenomena, and ammonium NH4+ ion trapping. Even if the ChemFET-based measurement system should be improved according to the soil(electrolyte)/sensor contact, such realizations and results show the ChemFET technology potentials for long-term analysis in soil, paving the way for future "in situ" approaches in the frame of modern farming.

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

ABSTRACTThe error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

Developments and Applications of Field-Effect Transistor

This review article delves into the development and future prospects of Field-Effect Transistors (FETs), tracing their evolution from the nascent theoretical concept proposed by Julius Lilienfeld in 1925. Over the years, FETs have traversed significant milestones, marking their progression from fundamental ideas to practical applications. Key among these milestones are the advent of the Metal-Oxide-Semiconductor FET (MOSFET), which revolutionized the electronics industry, the Fin FET, offering enhanced performance through three-dimensional structures, and the GateAll-Around FET (GAA-FET), promising even greater control and efficiency. It provides a systematic comparison of these technologies, dissecting their structural differences, evaluating performance metrics such as speed, power consumption, and scalability, and exploring their potential applications across diverse domains. While recent advancements in FET technology have primarily focused on structural innovations to mitigate the short channel effect, researchers are also actively exploring alternative avenues, including the use of novel materials and refined fabrication techniques, to further enhance FET performance and unlock new possibilities for electronic devices. This multifaceted approach underscores the dynamic and ever-evolving nature of FET technology, positioning it as a cornerstone for future advancements in electronics.

Voltage Differencing Buffered Amplifier Realisation Using 32 nm FinFET Technology and Universal Filter Applications

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

A Two-Step Dry Etching Model for Non-Uniform Etching Profile in Gate-All-Around Field-Effect Transistor Manufacturing.

The Gate-All-Around Field-Effect Transistor (GAAFET) is proposed as a successor to Fin Field-Effect Transistor (FinFET) technology to increase channel length and improve the device performance. The GAAFET features a complex multilayer structure, which complicates the manufacturing process. One of the most critical steps in GAAFET fabrication is the selective lateral etching of the SiGe layers, essential for forming the inner-spacer. Industry commonly encounters a non-uniform etching profile during this step. In this paper, a continuous two-step dry etching model is proposed to investigate the mechanism behind the formation of the non-uniform profiles. The model consists of four modules: anisotropic etching simulation, Ge atom diffusion simulation, Si/SiGe etch selectivity calculation and SiGe selective etching simulation. By calibrating and verifying this model with experimental data, the edge rounding and gradient etching rates along the sidewall surface are successfully simulated. Based on further examination of the influence of chamber pressure on the profile using this model, the inner-spacer shape is improved experimentally by appropriately reducing the chamber pressure. This work aims to provide valuable insights for etching process recipes in advanced GAAFETs manufacturing.

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Accelerating Linear Congruential Generators with Carbon Nanotube Field-Effect Transistors

Abstract In the era of technological advancements, safeguarding information privacy has become paramount across sectors like defense, finance, healthcare, and more. At the heart of these security measures lies cryptography, a field that necessitates the efficient processing and secure storage of data. Our project focuses on the optimization of Linear Congruential Generators (LCG), pivotal for cryptographic applications and pseudorandom number generation. Here it has been pioneered the implementation of LCG using Carbon Nanotube Field-Effect Transistor (CNTFET) technology, targeting the reduction of leakage power through the innovative application of sleep techniques. This advanced approach not only embodies a leap towards minimizing energy consumption but also enhances the overall performance and reliability of cryptographic systems. By integrating sleep modes into the CNTFET-based LCG design, our methodology significantly curtails leakage power without compromising the generator’s efficiency or output quality. The successful implementation and synthesis of this design, employing cutting-edge CNTFET technology, underscore the potential for substantial improvements in power efficiency while maintaining high standards of security and randomness essential for cryptographic algorithms.

Memristors with Monolayer Graphene Electrodes Grown Directly on Sapphire Wafers.

The development of the memristor has generated significant interest due to its non-volatility, simple structure, and low power consumption. Memristors based on graphene offer atomic monolayer thickness, flexibility, and uniformity and have attracted attention as a promising alternative to contemporary field-effect transistor (FET) technology in applications such as logic and memory devices, achieving higher integration density and lower power consumption. The use of graphene as electrodes in memristors could also increase robustness against degradation mechanisms, including oxygen vacancy diffusion to the electrode and unwanted metal ion diffusion. However, to realize this technological transformation, it is necessary to establish a scalable, robust, and cost-effective device fabrication process. Here we report the direct growth of high-quality monolayer graphene on sapphire wafers in a mass-producible, contamination-free, and transfer-free manner, using a commercially available metal-organic chemical vapor deposition (MOCVD) system. By taking advantage of this approach, graphene-electrode based memristors are developed, and all the processes used in the device fabrication incorporating graphene electrodes can be performed at wafer scale. The graphene electrode-based memristor demonstrates promising characteristics in terms of endurance, retention, and ON/OFF ratio. This work presents a possible and viable route to achieving robust graphene-based memristors in a commercially and technologically sustainable manner, paving the way for the realization of more powerful and compact integrated graphene electronics in the future.

FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design

In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Realization of a high-efficient GDI-based 4:2 compressor for sum of absolute difference detection in image and signal processing

A new 4:2 approximate compressor is designed based on gate diffusion input (GDI), which has 14 transistors and only 6 errors in its outputs. The integration of the GDI with the dynamic threshold (DT) overcomes the body effect by the selection of carbon nanotube field-effect transistors (CNTFET) technology. By embedding the proposed compressor in the 8-bit sum of absolute difference (SAD) system, an area of 284.6 µm2 is occupied and a reliable system for difference detection between two images and electrocardiogram (ECG) results. Considering the fair conditions of comparison, the proposed circuit has significant performance in terms of circuitry parameters such as power, delay, and figure of merits (FoMs). In terms of power-delay-product (PDP) and power-delay-area-product (PDAP) the proposed cell shows a saving of 27 % and 47 %, respectively. A 40 % improvement in terms of a FoM containing PDP and power signal-to-noise ratio (PSNR) compared to the closest competitor qualifies the proposed circuit over the other counterparts. The proposed cell has a high performance under the difference detection in images and ECGs.

Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits.

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities.

Achieving High-Performance Polymer-Wrapper-Free Aligned Carbon Nanotube Field-Effect Transistors Through Degradable Polymer Wrapping and Efficient Removal Techniques.

Semiconducting carbon nanotubes (s-CNTs) have emerged as a promising alternative to traditional silicon for ultrascaled field-effect transistors (FETs), owing to their exceptional properties. Aligned s-CNTs (A-CNTs) are particularly favored for practical applications due to their ability to provide higher driving current and lower contact resistance compared with individual s-CNTs or random networks. Achieving high-semiconducting-purity A-CNTs typically involves conjugated polymer wrapping for selective separation of s-CNTs, followed by self-assembly techniques. However, the presence of the polymer wrapper on A-CNTs can adversely impact electrical contact, gating efficiency, carrier transport, and device-to-device variations, necessitating its complete removal. While various methods have been explored for polymer removal, accurately characterizing the extent of removal remains a challenge. Traditional techniques such as absorption spectroscopy and X-ray photoelectron spectroscopy (XPS) may not accurately depict the remaining polymer content on A-CNTs due to their inherent detection limits. Consequently, the performance of FETs based on pure polymer-wrapper-free A-CNTs is unclear. In this study, we present an approach for preparing high-semiconducting-purity and polymer-wrapper-free A-CNTs using poly[(9,9-dioctylfluorenyl-2,7-dinitrilomethine)-(9,9-dioctylfluorenyl-2,7-dimethine)] (PFO-N-PFO), a degradable polymer, in conjunction with a modified dimension-limited self-alignment process (m-DLSA). Comprehensive transmission electron microscopy (TEM) characterizations, complemented by absorption and XPS characterizations, provide robust evidence of the successful near-complete removal of the polymer wrapper via a cleaning procedure involving acidic degradation, hot solvent rinsing, and vacuum annealing. Furthermore, top-gated FETs based on these high-semiconducting-purity and polymer-wrapper-free A-CNTs exhibit good performance metrics, including an on-current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω·μm, and negligible hysteresis, representing a significant advancement in the CNT-based FET technology.

Design and fabrication of S-band power amplifier for wireless sensor networks

This paper discusses the process of designing and manufacturing a wideband power amplifier operating in the S-band. To amplify a low power and broadband radio frequency signals from 2.1 GHz to 2.5 GHz, the proposed power amplifier uses a diagram of a two-stages amplification with peak offset amplification frequency 2.3 GHz. The power amplifier is designed with a center frequency difference of 2.2 GHz and 2.4 GHz respectively to achieve a bandwidth of 400 MHz. The proposed power amplifier (PA) uses RF transistor SHF-0589 using gallium arsenide heterostructure field-effect transistor (GaAs HFET) technology for high gain and low power consumption. The complete amplifier achieves power gain 21.1 dB inband 2.1-2.5 GHz and achieve maximum power gain of 22.5 dB at the frequency of 2.4 GHz; the output power rise up to 33 dBm; input reflection coefficient (S11) reaches -19.2 dB and output reflection coefficient reaches -17.2 dB. The designed amplifier circuit can be used for wireless sensor networks operating at S-band.

CNTFET-Based Single-Ended Fractional Order Colpitts Oscillator: Design, Simulation and Comparative Analysis

In this paper, we design and simulate a Single-Ended Colpitts Oscillator (CO) in integer and fractional order domains. The oscillators are realized in 32[Formula: see text]nm node conventional MOSFET and carbon nanotube field effect transistor (CNTFET) technologies. Therefore, four COs have been designed, simulated and rigorously compared. These include integer order conventional MOSFET-based CO, fractional order MOSFET-based CO, CNTFET-based integer order CO and CNTFET-based fractional order CO, all based on 32-nm technology nodes. The fractional order approach has been used as it results in better control over the phase and frequency of the oscillator. Herein, fractional order capacitors of various orders, used in realizing the fractional order COs, are realized and their frequency responses are studied. This is being done to ensure whether the designed pseudo-capacitances have fractional behavior or not in the desired frequency and phase spectrum. It has been observed that the variation of fractional order [Formula: see text] from 0.4 to 0.81 has resulted in a slight reduction of oscillation frequency from 1.68[Formula: see text]GHz ([Formula: see text]) to 1.351[Formula: see text]GHz ([Formula: see text]) keeping the pseudo-capacitance same at 0.3[Formula: see text]nF in MOS-based topology. Since the fractional order realization increases the circuit complexity and power consumption, therefore, CNTFET-based integer order as well as fractional order COs have been designed. The CNTFET-based fractional order CO retains the advantages of the fractional order domain as well as the power efficiency of CNTFETs. Further, it has been observed that integrating fractional-order capacitor (FOC) with the CNTFET CO results in a much larger constant phase zone (CPZ), an important performance measuring parameter. A rigorous comparative analysis of the four COs designed in this work has been performed.

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Advancements And Applications of Finfet Technology in Modern Semiconductor Engineering

This comprehensive study presents an in-depth analysis of Fin Field-Effect Transistor (FinFET) technology, a significant innovation in semiconductor technology, focusing on its structural attributes, applications, and future prospects. FinFETs, characterized by their distinctive fin-like channels, are pivotal in overcoming the limitations of traditional MOSFETs, particularly in the context of device miniaturization. The paper begins by exploring the basic theory and structural characteristics of FinFETs, emphasizing their enhanced control over short channel effects and reduced leakage currents in scaled-down devices. Attention is then directed towards the integration of FinFET technology in Static Random-Access Memory (SRAM), detailing how FinFETs contribute to improved stability and efficiency in memory storage. Another crucial application discussed is in the biomedical field, where FinFETs have facilitated the development of advanced instrumentation amplifiers and sensitive sensors, marking a leap in medical electronics. The paper concludes by addressing the challenges encountered by FinFETs as fabrication approaches the 5-7nm scale, including their physical and structural limitations. It also highlights ongoing research in structural modifications and material innovations like Gate-All-Around FETs and alternative materials, underscoring the continued evolution and relevance of FinFET technology in the ever-advancing semiconductor industry.

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.