Field Effect Transistor Technology Research Articles

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Carbon Nanotube Field Effect Transistor Technology for Power Reduction

Design of Low Power Ternary Logic Encoder and ADC using CNTFET

Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.

A New Approximate Sum of Absolute Differences Unit for Bioimages Processing

An inexact 6-transistor full adder (FA) cell is presented. It is low-power and gives full-swing outputs because of the applied gate diffusion input (GDI) along with the dynamic threshold (DT) techniques. The FA which has three errors is used in a 10-transistor inexact 4:2 compressor based on the stacking circuit idea. The implementation by a 16 nm carbon nanotube field-effect transistor (CNTFET) technology shows a small area of 0.027 lm2 and 0.045 lm2 for the FA and compressor, respectively. A new approximate sum of absolute differences (SAD) block is presented by the FA and compressor. The average power, power-delay-product (PDP), and peak signalto-noise ratio (PSNR) of the SAD are 6.80 mW, 33.86 nJ, and 42.98 dB, respectively, which confirm its efficiency for bioimages difference detection.

Performance comparison and analysis of silicon-based and carbon-based integrated circuits under VLSI

Since 1960, the semiconductor industry has invented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) technologies. Subsequently, the semiconductor-based integrated circuit industry has led a new generation of information revolution, driving the rapid development of various electronic circuit technologies worldwide. With the physical limitations of the silicon semiconductor process, Moores Law is also approaching its physical limit. In the search for new semiconductor materials, carbon nanotube semiconductors have become one of the candidate materials for new semiconductor materials due to their many advantages, and their many characteristic parameters are even better than those of silicon semiconductors of the same size. This article introduces the research status, performance characteristics, and comparison of silicon-based and carbon-based integrated circuits, as well as the current application scenarios of silicon-based and carbon-based integrated circuits in the industry, and the many problems encountered. Finally, this article analyses the future development direction of the integrated circuit industry and the possible challenges it may face.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Development and Fabrication of MOSFET-Based Radiation Dosimeter (RadFET) for Enhanced Performance in Space Missions

This work presents the development and fabrication process of a radiation dosimeter based on Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) technology, known as RadFET. The aim of this study is to determine the specifications of the RadFET sensor for use in space missions by the Egyptian Space Agency in SPNeX mission. We have successfully determined the sensor specifications, specified the required electronic components for readout circuits, and confirmed the correct operation of the RadFET device through device simulations and radiation-induced damage models. The fabrication process was conducted at Zewail City of Science, Technology and Innovation cleanroom facility, utilizing Sentaurus TCAD for device and process simulations. We have conducted fabrication experiments for phosphorus spin-on dopant application, dry oxide growth, and wet oxidation using water vapor bubblers. The dosimeter readout PCB fabrication and assembly phases have been successfully completed. The developed RadFET dosimeter holds great promise for radiation monitoring in space missions, ensuring enhanced safety and reliability of electronic systems.

Graphene's Potential in Electronic Devices: Characteristics, Applications, Challenges, And Solutions

This comprehensive overview explores the multifaceted world of graphene, a two-dimensional crystal structure composed of a single layer of carbon atoms, and its applications in electronic devices. The discussion begins with an introduction highlighting the remarkable potential of graphene in the field of electronics. Section 2 delves into the basic characteristics of graphene, including its atomic structure, excellent electronic properties, optical and thermal attributes, high conductivity, and mobility, as well as its mechanical strength and flexibility. It also briefly outlines the fundamental methods of graphene preparation. Section 3 delves into the application of graphene in electronic devices, covering topics such as graphene's role in Field Effect Transistors (FETs), including carrier control characteristics and the basic principles of FETs. Additionally, it explores the prospects of graphene in FET technology, its application in flexible electronic devices, and its integration into optoelectronic devices. Section 4 addresses the dilemmas and solutions faced by graphene electronic devices, such as issues related to the preparation process and stability, the impact of defects and impurities, and current solutions to overcome these challenges. Finally, the conclusion underscores the immense potential of graphene in revolutionizing electronic devices while recognizing the ongoing efforts for future innovations in this field.

Implementation of Taguchi Method in Improving the Logic Gates Performance based on Carbon Nanotube Field Effect Transistor Technology

The International Roadmap for Device and Systems (IRDS) 2022 has emphasized the potential of CNTFETs to replace CMOS technology. Therefore, the substitution of silicon with carbon nanotubes (CNTs) has the potential to open new possibilities for the semiconductor industry, due to their compact size and superior electrical properties. Thus, this project utilized Cadence Virtuoso software to develop an optimized CNTFET design using Taguchi method. In this design, the Taguchi method was implemented to determine the best combination of design parameter and material for optimum CNTFET performance. The design parameter and material that had been chosen were the diameter of carbon nanotube, dielectric material and oxide thickness. The optimized CNTFET model is implemented in circuit study to analyse the propagation delay and power consumption. Five circuits had been designed from the optimized CNTFET which are the inverter, AND, OR, NAND and NOR circuit. The Taguchi Optimization method resulted in significant reductions in the power- delay product (PDP) for all circuits examined, ranging from 7.9954% for the AND circuit to an exceptional 99.9622% for the inverter circuit. These findings highlight the potential for improved power efficiency and faster circuit operation when utilizing the Taguchi Optimization approach.

4:2 Compressor Design for Low Leakage Applications in FinFET Technology

ABSTRACT The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology for future systems. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart.

Comparing Unbalanced and Balanced CNTFET Ternary Adders and Multipliers with the Corresponding Binary Ones

This paper compares the performance of the ternary adders and multipliers using balanced and unbalanced set of values. We use the 1-trit adders to evaluate the two versions of a 4-trit propagate adder, which are comparedwith a 6-bit corresponding propagate adder. Similarly, we compare the two types of 2*2 trit multipliers with a3*3 bit multiplier. The simulations with a 32-nm Carbon Nanotuble Field-Effect Transistor (CNTFET) technology show that the binary adders and multipliers are more efficient than the ternary ones that compute the same amount of information

Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10[Formula: see text]nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7[Formula: see text]V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with [Formula: see text]% deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations.

Picosecond and high-power UV/Vis light pulsing using gallium nitride field-effect transistors: implementation and design evaluation

This paper discusses the development of cost-effective and high-performance picosecond and high-power light pulsers. The use of innovative gallium nitride field-effect transistor technology, in combination with meticulous electronic design and careful selection of light-emitting diodes or laser diodes for ultraviolet and visible spectral ranges, has resulted in superior characteristics compared to commonly used designs. The sub-ns design achieves pulse widths as low as 300 ps, with photon outputs ranging between 104-109 photons per pulse, over a wavelength range of 235-470 nm. Meanwhile, the high-power design achieves pulse widths as low as 1.8 ns, with photon outputs ranging between 107-1011 photons per pulse, and a wavelength range of 375-525 nm. The two designs complement each other in photon outputs, covering a dynamic range of almost ten orders of magnitude. This paper provides an evaluation of the electrical design and emitter selection of both pulsers, as well as their electrical and optical performance.

A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications

ABSTRACT Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (I ON /I OFF ) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at V DD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in I ON /I OFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending

This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder cells. Software simulations confirm the suitable quality of the final images according to the image quality evaluation criteria.

High-efficient and error-resilient gate diffusion input-based approximate full adders for complex multistage rapid structures

Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate Cout, approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications.

Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Adder for Bioimages Processing.

Approximate circuits are used in fault-tolerance applications, where carbon nanotube field-effect transistor (CNTFET) technology assists to achieve high performance. In this study, a new 8-transistor approximate full adder (FA) is designed and implemented using CNTFETs based on the gate diffusion input (GDI) technique. The FA is implemented in a ripple carry adder (RCA) and a 4-bit inexact subtractor for bioimages difference detection and finally stroke recognition. The non-full-swing outputs of the presented GDI cells are obviated by the dynamic threshold (DT) technique. The presented FA consumes a power of 2.0446 µW, while its power-delay-product (PDP) is 6.4536 fJ. Also, the superior results of peak signal-to-noise ratio (PSNR), power consumption, and PDP of the proposed subtractor are 30.866 dB, 9.642 µW, and 314.907 fJ, respectively. The FA has an area of 0.161 µm2 while the 4-bit subtractor occupies 2.18 µm2. The presented circuits show efficient performance for bioelectronics integrated circuits (ICs).

Parity Generators for Nanocommunication Systems Using QCA Nanotechnology

Quantum-dot cellular automata (QCA) nanotechnology has the capability to design highly-dense, ultra-low power, and high-speed digital circuits at ultra-deep sub-micron (ultra-DSM) level. QCA nanostructure provides a transistor-free operation that saves large energy dissipation as compared to the conventional metal oxide semiconductor field effect transistor (MOSFET) technology. In this paper, 3-input exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are presented using QCA cells. XOR and XNOR (XOR-XNOR) gates are further utilized to design the 2-, 3-, 4-, and 5-bit even and odd parity generators. The QCA-based 3-input XNOR gate is constructed using only 10 QCA cells and two clock phases. The target of the presented designs is to use the minimum count of QCA cells in a simplistic way to form the higher bit-size parity generators. The comparative analyses for the different performance metrics are showing that the developed designs are performing well for the cell count, latency, area, and layout cost as compared to the existing designs. Energy dissipation for the designs is calculated to check the energy efficiency by using the QCA Designer-E and QCA Pro tools.