Field-effect Transistor Structure Research Articles

High-Response, Self-Driving Infrared Photodetection Based on WS2-Graphene Heterostructure and Metal-Oxide-Semiconductor Field Effect Transistor Structure

High-Response, Self-Driving Infrared Photodetection Based on WS2-Graphene Heterostructure and Metal-Oxide-Semiconductor Field Effect Transistor Structure

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Reduction in density of interface traps determined by C-V analysis in III-nitride-based MOSHFET structure

An in situ metal-organic chemical vapor phase epitaxy is used to grow a complete AlGaN/GaN metal oxide semiconductor heterojunction field effect transistor (MOSHFET) structure, gated by a gallium oxide (Ga2O3) layer; we observed reduction in the interfacial trap density compared to its version wherein the Ga2O3 was grown ex situ, after breaking the vacuum, all else being the same. A remarkable decrease in the interfacial charge density for in situ MOSHFET structures in the range of 70%–88% for 10–30 nm oxide layer thickness and improvements in other electrical parameters required for high-performing devices were observed.

TMD material investigation for a low hysteresis vdW NCFET logic transistor

Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 µS µm−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.

Recent Progress of Exhaled Gas‐Based Diagnosis Based on Field Effect Transistor Sensors

AbstractExhaled breath‐based disease diagnosis is an ancient technique, and the application of this technique is rapidly developing for disease quick testing, such as viral infection, asthma, chronic kidney disease, and so on. Among the diagnostic tools, an exhaled breath‐based test has demonstrated the merits of being non‐invasive, convenient, quick, and comfortable. In this review, the exhaled breath diagnosis via the gaseous part of the breath is the major focus. First, the summary of state‐of‐art studies based on exhaled gas detection is described. Second, typical disease‐related exhaled gas and their measurements are described. Finally, the various structure of field effect transistor (FET)‐type sensors for gas‐based disease detection is discussed in detail. This review may inspire new research ideas and directions for applying FET‐type sensors to quick disease detection via the gaseous route.

New Approach for Enhancing Sensitivity in Liquid‐Gated Nanowire FET Biosensors Under Optical Excitation

AbstractThe results obtained for liquid‐gated (LG) nanowire (NW) field‐effect transistor (FET) sensors analyzed in divalent ion (MgCl2) solutions, which play a crucial role in the human body, are reported. Liquid‐gated NW FET sensors fabricated in‐house are investigated using I–V characteristics and noise spectroscopy in a wide range of voltages and different intensities of optical infrared irradiation. A new effect is revealed under the influence of external optical excitation. The effect allows for the control of characteristic times of single‐trap phenomena: capture time to a single trap, emission time from the trap, and its ratio represented by the dimensionless ratio parameter (R‐factor). These parameters enabled an improvement in sensor sensitivity. The findings open prospects for controlling charge states in LG NW FET structures to optimize new parameters for achieving ultrahigh sensitivity in biosensors.

Improved SOI-MESFET structures for enhanced efficiency and optimized DC/RF characteristics

ABSTRACT In this paper, two new silicon on insulator metal-semiconductor field effect transistor (SOI-MESFET) structures are presented. Two parallel layers of oxide and aluminium are added at the gate edge of these structures. Also, in the buried oxide part of the Aluminium Edge and Silicon-Well MESFET (AESW-MESFET) structure, a silicon well and two aluminium layers are added. Moreover, and to improve the DC and RF characteristics, as compared to the Conventional MESFET (C-MESFET) structure, a silicon well and a silicon layer are added in the box oxide section in the Silicon Edge and Silicon-Well MESFET (SESW-MESFET) structure. By these changes, the value of the breakdown voltage in the normal structure has increased from 15.8 V to 33.1 V and 30.9 V in the proposed AESW-MESFET and SESW-MESFET structures, respectively. In addition, the maximum output power has been associated with a significant increase of 4.44 and 5.24 times, respectively. Compared to the C-MESFET, the proposed structures reduce gate-source and gate-drain capacitors and significantly increases conductivity. The cut-off frequency values are increased from 19.3 GHz (the normal structure) to 37.3 GHz and 35 GHz (the proposed structures), and the maximum oscillation frequencies are increased from 80 GHz to 154 GHz and 102.3 GHz. Therefore, the results show that the proposed structures have good performance and the ability to work at high power and high frequency.

Exploring the ITO/PET Extended-Gate Field-Effect Transistor (EGFET) for pH Sensing.

In this project we investigated the extended-gate field-effect transistor (EGFET) structure used with ITO (Indium Tin Oxide)/PET (Polyethylene Terephthalate) sensitive films acting as the extended-gate part of an EGFET obtained from a combination of FETs from the CD4007 chip. We tested the device as a pH sensor by immersing the ITO/PET electrode in several chemical solutions of acidic and basic nature, including hydrogen peroxide, acetic acid, sulfuric acid, and ammonium hydroxide, at different concentrations. Using a Tektronix 4200A sourcemeter, we plotted the current-voltage (I-V) characteristics for the different chemical solutions, and we established a correlation to the pH changes. Results from the plotted I-V characteristics show a great dependance of the drain current (ID) on solution concentration. Furthermore, we measured the pH of each of the used solutions, and we established a relationship between the drain current and the pH value. Our results show a consistent decrease in the current with an increase in the pH value, although with different rates depending on the solution. The device showed high voltage sensitivity at 0.23 V per pH unit when tested in sulfuric acid.

Effect of parabolic structure potentials on electron mobility in AlxGa1-xAs quantum well based field effect transistor structure

Here, we theoretically calculate and analyze electron mobility μ in AlxGa1-xAs double parabolic and semi-parabolic quantum well (DPQW and DSPQW) based field effect transistor structures. We compute μ as a function of applied electric field F by considering ionized impurity (II) and alloy disorder (AL) screened scattering potentials (VscrII/AL) and show that μ(DPQW) > μ (DSPQW). The symmetric property of VscrII/AL makes μ to vary symmetrically around F = 0 at which two subbands are occupied. The shape of the DSPQW structure potential, compared to DPQW, causes the subband wave functions ψ0 and ψ1 to lie nearer and also penetrate more into the central barrier. Accordingly, the II-scattering is reduced due to increased distance of the electrons from the ionized donors (lying in the side barriers), while AL-scattering is enhanced through increased scattering in the central barrier. As a result, we obtain for F = 0, μII (DSPQW) > μII (DPQW) and μAL (DSPQW) < μAL (DPQW). Further, we show that μ enhances in DPQW by increasing design parameters such as well width, spacer width, and central barrier width. However, μ reduces with the increase in alloy concentrations inside the well through intersubband interaction. The obtained results reflect the suitability of parabolic potential based quantum well structures in emerging optoelectronic devices to enhance the transport and optical properties.

Simulation on the Effect of Channel Thickness on the Performance of Multi-Bridge Channel Field-Effect Transistor

A Multi-Bridge Channel Field-Effect Transistor (MBCFET) structure has been designed and simulated to characterize its electrical performance. An MBCFET is a device designed to bridge single-channel FETs, allowing more flexibility with signal routing and power management in complex designs. However, MBCFET suffers from Short Channel Effects which degrade its performance. Channel thickness is another important parameter that affect the performance of MBCFETs. Thus, the impact of channel thickness variation on MBCFET performance is investigated in this project. The electrical characteristic of MBCFET such as its threshold voltage (Vth), subthreshold swing (SS), on-state current (Ion), and off-state current (Ioff) were obtained and analyzed by using the TCAD simulation tool. Comparing the simulation results to published results indicated that the difference between the results was less than 5% for various parameters. The second part of the simulation work shows that as the channel thickness of an MBCFET increases, Vth decreases, Ion increases, and SS decreases. However, when the channel thickness is too thin, SS increases significantly, which leads to the device consuming higher power with lower performance.

Feature extractions from transfer characteristics of hybrid GO FETs for selective detection of volatile organic compounds

The current work concerns a new strategy for selective classifications of multiple volatile organic compounds (VOCs) by using an array of field effect transistor (FET) type sensors and extraction of device-specific features from transfer characteristics of the FET-sensors to use in classification algorithm(s). A few layered graphene oxide (GO) was used as the base channel materials which was then functionalized very precisely with different metal oxides (WO3, TiO2) and metals (Au, Pd) nanoforms to construct an array of five FET structure sensors on SiO2/Si platform. The deviation in Id-Vgs characteristics in different VOCs were accounted with a distinctive features. The features were organized based on their importance score and used to construct different feature matrices. A minimum four sensors and six features were required to successful classification of seven VOCs by linear discriminant analysis (LDA). The classification accuracy was tested with supportive vector machine (SVM) classifier and it was 92.86%.

High-Frequency Performance Characteristics of the Double-Gate Schottky Barrier Tunnel Field Effect Transistor in Analog and Radio-Frequency Applications

In this paper, a novel structure of Double Gate Schottky Barrier Tunnel Field Effect Transistor (DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) and two gate metals with an HfO2. Silvaco-TCAD simulator has been used for investigating the analog and radio frequency performance of the DG-SBTFET. The proposed device (DG-SBTFET) is compared with the conventional devices in terms of electrical parameters including ION current, ION/IOFF ratio, RF performance including transconductances (gm), cut-off frequency (f T ), transit time (r), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Further, we simulate the linearity characteristics of the DG-SBTFET device is compared it with other conventional devices, including the second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), and third-order input intercept point (IIP3). Hence, the proposed device (DG- SBTFET) is suitable for low-power and high-frequency applications.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Electrical properties of a low-temperature fabricated Ge-based top-gate MOSFET structure with epitaxial ferromagnetic Heusler-alloy Schottky-tunnel source and drain

We show electrical properties of a Ge-based top-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure with epitaxial ferromagnetic Heusler alloy/Ge Schottky-tunnel contacts, fabricated with a low-temperature gate-stack process. For shaping the Ge-MOSFET with the ferromagnetic source and drain (S/D) contacts, we use a combination process of Ar+ ion milling and reactive ion etching (RIE). As a consequence of the formation of a gate stack (SiO2/GeO2) using a process temperature of 240 °C, we demonstrate inversion channel MOSFETs with a low gate-voltage operation (VG ∼5 V). Furthermore, we achieve a relatively high field-effect mobility (μFE) of ∼300 cm2/Vs compared to those in a Si-based back-gate spin-MOSFET reported previously [Phys. Rev. B 102, 035305 (2020).]. This study will open a way for developing a Ge-based top-gate spin-MOSFET on the Si platform.

Phase Transition Field Effect Transistor Observed in an α-(BEDT-TTF)2I3 Single Crystal

The metal–insulator transition induced by the gate electric field in the charge order phase of the α-(BEDT-TTF)2I3 single-crystal field-effect transistor (FET) structure was clearly observed near the phase transition temperature. An abrupt increase in the electrical conductance induced by the applied gate electric field was evident, which corresponds to the partial dissolution of the charge order phase triggered by the gate electric field. The estimated nominal dissolved charge order region (i.e., the gate-induced metallic region) was overestimated in 130–150 K, suggesting additional effects such as Joule heating. On the other hand, in the lower temperature region below 120 K, the corresponding dissolved charge order was several monolayers of BEDT-TTF, suggesting that it is possible to dissolve the charge order phase within the bistable temperature region.

Comparison of Carrier Deflection between MAG-TFET and MAG-FinFET

This paper is a comparison of the carrier deflection mechanism of a new magnetic sensor structure between the tunneling Field Effect Transistor (TFET) structure and the FinFET structures so-called MAG-TFET and MAG-FinFET.The device relies on carrier deflection from magnetically induced forces. The MAG-TFET current is caused by electron tunneling and drifting through the bulk under gate while the MAG-FinFET current is caused by the drift channel carrier from the inversion layer induced by gate voltages and there is also a bulk current beneath the substrate. The carrier deflection of the device is due to the current in the induced channel and current in the bulk. From the results, carrier deflection in the induced channel is better than in the bulk. The device sensitivity depends on the proportion of these two currents.

Minority carrier diffusion length in interface-confined PbS colloidal quantum dot (CQD): Effect of CQD surface modification on diffusion length in ultrathin PbS CQD films

Photocurrent microscopy (PCM) is a versatile tool for probing charge carrier transport associated with energy band bending at an interface. For the first time, we report the ligand-dependent electronic properties of interface-confined colloidal quantum dots (CQDs) near a metal electrode and gate dielectric layers using ultrathin lead sulfide (PbS) CQD films embedded in field effect transistors (FETs). We have compared the minority carrier (electron) diffusion length (MCDL) of ultrathin PbS CQD films treated with 1,2-ethanedithiol (EDT) and ammonium sulfide ((NH4)2S) using a bottom-contact FET structure in combination with PCM. We found that the MCDL was greater in the EDT-treated PbS CQDs than in the (NH4)2S-treated PbS CQDs. The MCDL at the 2D carrier accumulation layer was observed to depend on the concentration of the majority carrier (hole). During effective electrical channel formation by electrical gating, the MCDL decreased with hole accumulation (decreasing gate voltage) in the p-channel (NH4)2S-treated PbS CQD FET, whereas it remained similar in the EDT-treated PbS CQD FET. The effect of the majority carrier concentration on the MCDL was more pronounced in the (NH4)2S-treated sample than in the EDT-treated sample. The difference in the MCDL is attributed to a difference in the surface trap density caused by different ligand treatments.

Technology of MISFET with SiO2/BaTiO3 System as a Gate Insulator

The properties of barium titanate (BaTiO3, BT), such as high dielectric constant and resistivity, allow it to find numerous applications in the field of microelectronics. In this work silicon metal-insulator-semiconductor field effect transistor (MISFET) structures with BaTiO3 thin films (containing La2O3 admixture) acting as gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO3 + La2O3 (2% wt.) target. In the paper transfer and output I−V, transconductance and output conductance characteristics of the obtained transistors are presented and discussed. Basic parameters of these devices, such as threshold voltage (VTH) are determined and discussed.

Single silicon synaptic device for stochastic binary spike-timing-dependent plasticity

In this paper, we present a single silicon synaptic device that enables stochastic binary spike-timing-dependent plasticity. The single silicon synaptic device, which is similar to a conventional metal-oxide-semiconductor field-effect transistor structure, is implemented using standard complementary metal-oxide-semiconductor technology. The stochastic nature of the feedback mechanism induced by weak impact ionization is experimentally demonstrated. Because of probabilistic dynamics in the feedback mechanism, the single silicon synaptic device features stochastic binary spike-timing-dependent plasticity.

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate.

A complementary doped source-based reconfigurable Schottky diode (CDS-RSD) is proposed for the first time. Unlike other types of reconfigurable devices that have source and drain (S/D) regions with the same material, this has a complementary doped source region as well as a metal silicide drain region. Compared to three-terminal reconfigurable transistors, which have both the program gate and control gate, the proposed CDS-RSD does not have a control gate but only a program gate for reconfiguration operation. The drain electrode of the CDS-RSD is not only the output terminal of the current signal but also the input terminal of the voltage signal. Therefore, it is a reconfigurable diode based on high Schottky barriers for both the conduction band and valence band of silicon, which formed on the interface between the silicon and drain electrode. Therefore, the CDS-RSD can be regarded as the simplification of the reconfigurable field effect transistor structure on the premise of retaining the reconfigurable function. The simplified CDS-RSD is more suitable for the improvement of logic gate circuit integration. A brief manufacture process is also proposed. The device performance has been verified through device simulation. The performance of the CDS-RSD as a single-device two-input equivalence logic gate has also been investigated.