Performance Of Field-effect Transistors Research Articles

Effect of biaxial misfit strain on properties of ferroelectric double gate negative capacitance transistors

In order to continue Moore’s law, the reduction of power consumption has received much attention. It is necessary to develop steep devices that can overcome the “Boltzmann tyranny” and solve the problem of high power consumption of integrated circuits. Negative capacitance field-effect transistors are one of the most promising candidates in numerous steep devices. Strain engineering has been widely studied as an effective means of regulating the properties of ferroelectric thin films. However, the influence of strain on the performance of negative capacitance field-effect transistor has not been clear so far. Therefore, in this work, an analytical model of double gate negative capacitance field-effect transistor (DG-NCFET) regulated by biaxial misfit strain is proposed. Using this model, we investigate the influences of ferroelectric layer thickness and biaxial misfit strain on electrical properties of PbZr<sub>0.5</sub>Ti<sub>0.5</sub>O<sub>3</sub> (PZT)-based and CuInP<sub>2</sub>S<sub>6</sub> (CIPS)-based negative capacitance field-effect transistors (NCFETs), respectively. The results show that for the negative capacitance field-effect transistor based on PbZr<sub>0.5</sub>Ti<sub>0.5</sub>O<sub>3</sub>, when the ferroelectric layer thickness is increased or the compression strain is applied, the subthreshold swing and conduction current are improved, but the tensile strain has the opposite effect. For the negative capacitance field-effect transistor based on CuInP<sub>2</sub>S<sub>6</sub>, its performance is improved when the thickness of the ferroelectric layer is increased or the tensile strain is applied, but the device lags behind under the compressive strain. It is found that the CIPS-based NCFET exhibits better performance than PZT-based NCFET at low gate voltages.

In situ tuning of the performance of polymer field-effect transistors by soft plasma etching

The subthreshold swing, threshold voltage and hysteresis of PCDTPT OFETs can be in situ tuned by soft plasma etching.

Locally Thinned, Core-Shell Nanowire-Integrated Multi-gate MoS2 Transistors for Active Control of Extendable Logic.

Field-effect transistor (FET) devices with multi-gate coupled structures usually exhibit special electrical properties and are suitable for fabricating multifunctional devices. Among them, the 1D nanowire gate configuration has become a promising gate design to tailor 2D FET performances. However, due to possible short circuiting induced by nanowire contact and the high requirement for precision manipulation, the integration of multi-nanowires as gates in a single 2D electronic system remains a grand challenge. Herein, local laser--thinned multiple core-shell SiC@SiO2 nanowires are successfully integrated into MoS2 transistors as multi-gates for active control of extendable logic applications. Nanowire gates (NGs) locally enhance the carrier transportation, and the use of multiple NGs can achieve designed band structures to tune the performance of the device. For core-shell structures, a semiconducting core is used to introduce a gate bias, and the insulating shell provides protection against short circuiting between NGs, facilitating nanowire assembly. Furthermore, a global control gate is introduced to co-tune the overall electrical characteristics, while active control of logic devices and extendable inputs are achieved based on this model. This work proposes a novel nanowire multi-gate configuration, which provides possibilities for localized, precise control of band structures and the fabrication of highly integrated, multifunctional, and controllable nano-devices.

500 °C operation of β-Ga2O3 field-effect transistors

We demonstrated 500 °C operation of field-effect transistors made using ultra-wide bandgap semiconductor β-Ga2O3. Metal–semiconductor field-effect transistors were fabricated using epitaxial conductive films grown on an insulating β-Ga2O3 substrate, TiW refractory metal gates, and Si-implanted source/drain contacts. Devices were characterized in DC mode at different temperatures up to 500 °C in vacuum. These variable-temperature measurements showed a reduction in gate modulation of the drain current due to an increase in gate leakage across the gate/semiconductor Schottky barrier. Devices exhibited a reduction in transconductance with increasing temperature; despite this, drain current increased with temperature due to a reduction in threshold voltage caused by the de-trapping of electrons from deep-level traps. Devices also showed negligible change in semiconductor epitaxy and source/drain contacts, hence demonstrated recovery to their room-temperature electrical properties after the devices were tested intermittently at different high temperatures in vacuum. The mechanism of gate leakage was also explored, which implicated the presence of different conduction mechanisms at different temperatures and gate electric fields.

Wafer‐Scale PLD‐Grown High‐κ GCZO Dielectrics for 2D Electronics (Adv. Electron. Mater. 12/2022)

High-κ Gate Dielectrics In article number 2200580, Jing Yu, Wei Han, Francis Chi-Chung Ling, and co-workers prepare large-size (Ga, Cu) co-doped ZnO films with super-high dielectric constant (κ > 50) and good homogeneity by a pulsed laser deposition (PLD) method. The performance of SnS2 field-effect transistor reveals that high-κ Al2O3/GCZO gate dielectric stack is suitable for 2D electronic devices. The success in fabrication of GCZO films not only show higher κ than other conventional dielectrics in terms of compatibility to CMOS processes, but also keep their comparative advantages in the fabrication of high-performance electronic devices over conventional dielectrics.

Macroscopic analysis and design of Si HFGFET gas sensor for sensitive gas detection

In this study, we investigate gas sensing performance of horizontal floating-gate field-effect transistor (HFGFET) gas sensors having different FET channel width and length, and the number and length of FG fingers using both technology computer-aided design (TCAD) device simulation and actual gas sensing measurement. The HFGFET gas sensors have a control-gate (CG) and a FG, which are horizontally interdigitated. An indium oxide (In2O3) film is locally deposited between the CG and FG to be used as a sensing layer. Utilizing a simplified equivalent circuit and electrical characteristics of the HFGFET gas sensors, we define a new parameter G, which represents a magnitude of gas sensitivity. The effect of channel width and length, and the number and length of FG fingers of the HFGFET gas sensors on gas sensitivity is first investigated by TCAD device simulation, and then verified by NO2 and H2S gas sensing measurement.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays.

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (Ion) of 800 μA/μm and a peak transconductance (gm) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm2 V-1 s-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

Impact of Narrowing Density of States in Semiconducting Polymers on Performance of Organic Field-Effect Transistors.

To improve the performance of organic field-effect transistors (OFETs) employing π-conjugated polymers, a basic understanding of the relationships between the material properties and device characteristics is crucial. Although the density of states (DOS) distribution is one of the essential material properties of semiconducting polymers, insights into how the DOS shape affects the mobility (µ), subthreshold swing (S), and contact resistance (RC ) in OFETs remain lacking. In this study, by combining sensitive DOS measurements and multilayered OFET structures, it is experimentally demonstrated that narrower DOS widths in the polymer channels lead to higher µ, smaller S, and lower RC . By contrast, variation of the DOS in the bulk layer does not affect the performance. These results demonstrate a direct relationship between the polymer properties and OFET performance and highlight the importance of controlling the DOS width in π-conjugated polymers.

DC/RF performance and temperature sensitivity of ground-plane based JLTFET

ABSTRACT This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high- gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage (), and ratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here.

Performance Analysis of Reverse T-Shaped Tunnel Field Effect Transistor (RT-DG-TFET) Based Lable–Free Dielectric Modulation Detection of SARS-CoV-2 Virus

In this paper the performance of Reverse T-Shaped Double gate Tunnel field effect transistor is investigated (RT-DG-TFET)with respect to different bio molecules for application as biosensor. The proposed device is built in order to overcome the limitations of short channel effects (SCEs) in MOSFET devices. The recent outbreak due to Corona virus demanded the requirement of a lable free, highly sensitive, quick and meticulous biosensor for the detection of SARS-CoV-2 virus. This device study records the lable free electrical detection of SARS-CoV-2 virus using RT-DG-TFET that detects the virus because of the electrical properties (dielectric constant) of different bio molecules like protein, biotin, air, strepta, APTES, DNA etc. These are studied by using different dielectric modulation techniques in biosensor application. The etched nano-cavity implanted under the gate electrode first immobilizes the SARS-CoV-2 virus, which is subsequently used to identify it. The sensitivity and different analog/RF parameters are also investigated for different bio molecules. All these simulations are investigated in TCAD Sentaurus simulator.

Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials.

Two-dimensional (2D) semiconductors have been considered as promising candidates to fabricate ultimately scaled field-effect transistors (FETs), due to the atomically thin thickness and high carrier mobility. However, the performance of FETs based on 2D semiconductors has been limited by extrinsic factors, including high contact resistance, strong interfacial scattering, and unintentional doping. Among these challenges, contact resistance is a dominant issue, and important progress has been made in recent years. In this review, the Schottky-Mott model is introduced to show the ideal Schottky barrier, and we further discuss the contribution of the Fermi-level pinning effect to the high contact resistance in 2D semiconductor devices. In 2D FETs, Fermi-level pinning is attributed to the high-energy metal deposition process, which would damage the lattice of atomically thin 2D semiconductors and induce the pinning of the metal Fermi level. Then, two contact structures and the strategies to fabricate low-contact-resistance short-channel 2D FETs are introduced. Finally, our review provides practical guidelines for the realization of high-performance 2D-semiconductors-based FETs with low contact resistance and discusses the outlook of this field.

Charge Transport Capabilities of Dibenzo[n]phenacenes (n = 5–7): Influence of Trap States and Molecular Packing

A high carrier transport capability with strong π–π interactions is expected to result from the extension of π conjugation in small molecules. This is an important factor to create promising molecules, leading to the development of high-performance and new applications in organic electronic devices. We systematically demonstrate the charge transport capability and trap density of states in dibenzo[n]phenacenes (DBnPs) (n = 5–7) with a hybrid π structure between the phenacene and acene cores. A DB6P field-effect transistor (FET) achieves a relatively high-field-effect mobility beyond 2 cm2 V–1 s–1, which indicates excellent FET performance in comparison with DB5P and DB7P. The calculated charge-transfer integrals based on the crystal structure and the distribution of the trap density of states confirm the superior transport capability and FET properties in DB6P. We demonstrate that molecules with C2h symmetry result in high crystallinity and close packing in crystals, leading to high-performance FETs.

A comprehensive analysis and performance comparison of CombFET and NSFET for CMOS circuit applications

The performance of comb-like channel field effect transistor (CombFET) and nanosheet FET (NSFET) is addressed at both device and circuit levels at the 3-nm node. The CombFET is realized by combining both FinFET and NSFET structures in the channel area. At the device level, the DC, analog/RF figures of merit (FOMs) are analyzed in detail. From simulations, it is observed that the on current (ION) is enhanced by 42% from NSFET to CombFET at the same off current (IOFF) of 250 pA under the same footprint (FP). CombFET's improvement over NSFET is the result of the channel's wider effective width. Further, an improvement of 30% in cut-off frequency (fT) and a decrement of 20% in intrinsic delay (τ) is noticed from NSFET to CombFET. On top of that dimensional impact on the electrical performance of CombFET analysed in detail. The CMOS circuit behaviour for ring oscillator (RO) is studied using the Verilog-A model for both FETs in the CADENCE tool. An oscillation frequency (fOSC) of 111.9 GHz and 82.7 GHz was noticed for CombFET and NSFET, respectively. Thus, the analyses demonstrate that CombFET offers superior performance over NSFET without increasing the FP.

Large area polymer semiconductor sub-microwire arrays by coaxial focused electrohydrodynamic jet printing for high-performance OFETs

Large area and highly aligned polymer semiconductor sub-microwires were fabricated using the coaxial focused electrohydrodynamic jet printing technology. As indicated by the results, the sub-microwire arrays have smooth morphology, well reproducibility and controllable with a width of ~110 nm. Analysis shows that the molecular chains inside the sub-microwires mainly exhibited edge-on arrangement and the π-stacking direction (010) of the majority of crystals is parallel to the long axis of the sub-microwires. Sub-microwires based organic field effect transistors showed high mobility with an average of 1.9 cm2 V−1 s−1, approximately 5 times higher than that of thin film based organic field effect transistors. In addition, the number of sub-microwires can be conveniently controlled by the printing technique, which can subsequently concisely control the performance of organic field effect transistors. This work demonstrates that sub-microwires fabricated by the coaxial focused electrohydrodynamic jet printing technology create an alternative path for the applications of high-performance organic flexible device.

Sn-Based Perovskite Halides for Electronic Devices.

Because of its less toxicity and electronic structure analogous to that of lead, tin halide perovskite (THP) is currently one of the most favorable candidates as an active layer for optoelectronic and electric devices such as solar cells, photodiodes, and field-effect transistors (FETs). Promising photovoltaics and FETs performances have been recently demonstrated because of their desirable electrical and optical properties. Nevertheless, THP's easy oxidation from Sn2+ to Sn4+ , easy formation of tin vacancy, uncontrollable film morphology and crystallinity, and interface instability severely impede its widespread application. This review paper aims to provide a basic understanding of THP as a semiconductor by highlighting the physical structure, energy band structure, electrical properties, and doping mechanisms. Additionally, the key chemical instability issues of THPs are discussed, which are identified as the potential bottleneck for further device development. Based on the understanding of the THPs properties, the key recent progress of THP-based solar cells and FETs is briefly discussed. To conclude, current challenges and perspective opportunities are highlighted.

Tafel-Kinetics-Controlled High-Speed Switching in a Electrochemical Graphene Field-Effect Transistor.

Graphene field-effect transistors (FETs) have attracted tremendous attention owing to the single-atomic-layer thickness and high electron mobility for potential applications in next-generation electronics. With regards to switching methodology, the electric-field-induced metal-insulator transition offers a new strategy to produce a large on/off current ratio through reversible electrochemical hydrogenation of the graphene channels. Therefore, the performance of such electrochemical graphene FETs greatly relies on the kinetics of hydrogenation reaction. Here, we show that the switching time can be systemically controlled by the applied gate voltages and geometries of graphene channels. The turn-on and turn-off time display an exponential dependence on the gate voltages, manifesting the dominated Tafel-form kinetics of hydrogenation reaction in a two-dimensional limit. Moreover, the turn-off time is inversely proportional to the channel width but independent of the length, while the turn-on time relies on both the width and length, as well as the off-state gate voltage and duration. Our work improves the response time to the magnitude of tens of microseconds and advances the application of graphene-based electronic devices.

Investigating Gate Interface Traps in β-Ga2O3 Field Effect Transistors (MOSFETs) By Using the Transfer Length Method (TLM) and UV Exposure

Beta-gallium oxide (β-Ga2O3) is a promising ultra-wide bandgap semiconductor for high power electronic applications due to its high theoretical critical field of 8 MV/cm, and Baliga figure of merit (BFOM) of ~3300, 3 – 10 times larger than current state-of-the-art wide bandgap semiconductors. β-Ga2O3 field-effect transistors (FETs) have been explored for both high power and radio frequency (RF) operation, but with relatively high parasitic resistances. A method is developed to determine the contact, series, and channel resistances in depletion mode β-Ga2O3 MOSFETs. The Al2O3-β-Ga2O3 interface is primarily important in the performance of β-Ga2O3 FETs due to charge trapping. Measurements will be performed with UV and visible light radiation to study the role of trap states on the FET resistances and device performance.Here, we report on using a modified transfer length method (TLM) to determine the contact, series, and channel resistances from planar, depletion-mode β-Ga2O3 FETs. The results are compared with respect to conventional TLM structures fabricated on the same wafer. The β-Ga2O3 FETs and TLM structures are fabricated on a (010) semi-insulating β-Ga2O3 substrate. The channel layer is a 50 nm Si-doped epi-layer with a target concentration of 2.4 x 1018 cm-3. A Ti/Al/Ni/Au metal stack is deposited and annealed to form Ohmic contacts. The gate dielectric is composed of atomic layer deposition-grown aluminum oxide (Al2O3, 20 nm). The structures have a constant gate length, LG, of 1.94 μm, while the total source-drain spacing, LSD, varies as 3μm, 8 μm, and 13 μm. Transfer characteristics were measured at room temperature and low drain-source voltage, VDS, of 0.01 V. The threshold voltage, VTH, was determined to be » -4V for all MOSFET devices. Measurements were performed in the dark or under UV (265 nm, 2.8 W/cm2) exposure.Conventional TLM structures were measured in the dark and with UV exposure, and a 40% decrease in the sheet resistance was observed when exposed to UV. We attribute this change to an increase in the carrier concentration from photo-generated electrons due to trap states within the β-Ga2O3. We also performed I-V measurements of the FETs in the dark and observed hysteresis behavior with respect to gate-source voltage, VGS, which we attribute to trapped charge at the Al2O3-β-Ga2O3 interface. Using the TLM method, we developed a methodology to extract the β-Ga2O3 MOSFET channel sheet resistances within the gated (Rsh,G) and ungated (Rsh) regions as a function of VGS. We observe a significant decrease in Rsh,G from 288 ± 14 kΩ sq-1 to 7.6 ± 0.38 kΩ sq-1 as VGS varies from -3 V to 3 V. The sheet resistance in the ungated regions, Rsh, shows a negligible change from 28 ± 1.4 kΩ sq-1 above a VGS of -1.8 V, comparable to that of the conventional TLM structures, but begins to increase with more negative VGS, reaching 90 ± 4.5 kΩ sq-1 at a VGS of -3 V. The VGS dependence of Rsh is due to complicated current flow mechanisms when the depletion region is large, which is not considered in this model. We will extend the study by performing I-V measurements with UV and visible light radiation to observe any effect of traps at the Al2O3-β-Ga2O3 interface has on Rsh and Rsh,G.

Tailoring the density of carbon nanotube networks through chemical self-assembly by click reaction for reliable transistors

Semiconducting single-walled carbon nanotubes (sc-SWNTs) are attracting considerable interest for use as active layers in various electronic applications such as field-effect transistors (FETs) because of their extremely high intrinsic charge carrier mobility and solution processability at low costs. However, it is challenging to achieve a constant sc-SWNT density for ensuring commercial-level, uniform performance in FETs based on random-network SWNT films formed by solution processing. This paper reports a facile method for sorting sc-SWNT and precisely controlling the density of random-network sc-SWNT films by azide-functionalized polymer. The chemical self-assembly of SWNTs is performed between azide-functionalized polymer-wrapped sc-SWNTs and alkyne-based substrate via click reaction. A high-purity sc-SWNT ink is obtained by the conjugated polymer wrapping method using an azide-functionalized polyfluorene in methylcyclohexane. The sc-SWNTs are then chemically bound to a substrate with an alkyne adhesive layer through a Cu-catalyzed azide-alkyne cycloaddition reaction. FETs with dense and uniform SWNT films with a linear density of 30 (±2) tubes μm−1 exhibit markedly high hole mobility of up to 25.4 cm2 V−1 s−1 and excellent performance uniformity. Furthermore, the SWNT films anchored on the substrates are highly resistant to exogenous disruptions, such as sonication in organic solvents, leading the great potential for applications such as biosensors that require strong adhesive strength.

The Effect of Amino-Phosphate Interactions on the Biosensing Performance of Enzymatic Graphene Field-Effect Transistors.

The interaction between polyamines and phosphate species is found in a wide range of biological and abiotic systems, yielding crucial consequences that range from the formation of supramolecular colloids to structure determination. In this work, the occurrence of phosphate-amino interactions is evidenced from changes in the electronic response of graphene field effect transistors (gFETs). First, the surface of the transistors is modified with poly(allylamine), and the effect of phosphate binding on the transfer characteristics is interpreted in terms of its impact on the surface charge density. The electronic response of the polyamine-functionalized gFETs is shown to be sensitive to the presence of different phosphate anions, such as orthophosphate, adenosine triphosphate, and tripolyphosphate, and a simple binding model is developed to explain the dependence of the shift of the Dirac point potential on the phosphate species concentration. Afterward, the impact of phosphate-amino interactions on the immobilization of enzymes to polyamine-modified graphene surfaces is investigated, and a decrease in the amount of anchored enzyme as the phosphate concentration increases is found. Finally, multilayer polyamine-urease biosensors are fabricated while increasing the phosphate concentration in the enzyme solution, and the sensing properties of the gFETs toward urea are evaluated. It is found that the presence of simple phosphate anions alters the nanoarchitecture of the polyelectrolyte-urease assemblies, with direct implications on urea sensing.

Effects of S-vacancy on electrical performance of monolayer TMD nanoribbons field-effect transistor

In this paper, the electrical properties of a FET based on nanoribbon of transition metal dichalcogenides in the presence of S-vacancy are investigated. The transition metal dichalcogenides (MoS2, MoSe2, WS2, and WSe2) monolayer is utilized as the channel for the FET. The non-equilibrium Green’s function (NEGF) along with the tight-binding method has been employed to study the electrical properties. The local density of states for pristine and defective ribbons are compared and the creation of mid-gap states due to S-vacancy is explored. The I-V characteristic of this FET is investigated. The increasing S-vacancy decreases ON-current whereas, leads to the increment of OFF-current. The considering 1.75% vacancy can decline ON-current 12 times for WSe2 and increases OFF-current 35 times for MoSe2.