Field-effect Transistor Devices Research Articles

The electronic and interfacial properties of a vdW heterostructure composed of penta-PdSe2and biphenylene monolayers

The vdW PdSe2/biphenylene network heterostructure withn-type Schottky contact and negative band-bending is theoretically designed to carry current in n-channel field effect transistor devices.

Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device

Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device

Tunnel field effect transistor device structures: A comprehensive review

Downscaling of metal oxide semiconductor field effect transistors (MOSFET) has resulted in increased short channel effects (SCEs), off-leakage current and subthreshold swing. At room temperature, the minimum subthreshold swing for MOSFETs is 60 mV/dec. So, MOSFET is not suitable for the deep submicron regime. A new device structure is being investigated to overcome the limitations of MOSFETs. The tunnel field effect transistor is the new emerging device (TFET). TFETs are the most suitable candidate for low power applications due to their superior performance, such as low power dissipation, low leakage current, and subthreshold swing (SS) less than 60 mV/dec. Ambipolar effect is the main cause of high Ioff current, this effect can be reduced by the asymmetry in structure and varied doping in source and drain. As a result, the Ioff current in the TFET may be reduced and the Ion/Ioff current ratio can be increased. TFET is a simple p-i-n structure with reversed bias at the gate terminal and works on the principle of the band to band tunneling (BTBT). The basic structure of TFET also suffers from low Ion current. However, with the variation of physical parameters in structure, the Ion current can be improved. This paper reviews the physical parameters of TFET and their impact as well as different structures of TFET like surface tunnel transistors, p-i-n structure TFET, Junctionless TFET, and Dual gate TFETs, Heterojunction TFETs, Vertical TFETs, PNPN TFET, and Nanowire TFET.

Locally Thinned, Core-Shell Nanowire-Integrated Multi-gate MoS2 Transistors for Active Control of Extendable Logic.

Field-effect transistor (FET) devices with multi-gate coupled structures usually exhibit special electrical properties and are suitable for fabricating multifunctional devices. Among them, the 1D nanowire gate configuration has become a promising gate design to tailor 2D FET performances. However, due to possible short circuiting induced by nanowire contact and the high requirement for precision manipulation, the integration of multi-nanowires as gates in a single 2D electronic system remains a grand challenge. Herein, local laser--thinned multiple core-shell SiC@SiO2 nanowires are successfully integrated into MoS2 transistors as multi-gates for active control of extendable logic applications. Nanowire gates (NGs) locally enhance the carrier transportation, and the use of multiple NGs can achieve designed band structures to tune the performance of the device. For core-shell structures, a semiconducting core is used to introduce a gate bias, and the insulating shell provides protection against short circuiting between NGs, facilitating nanowire assembly. Furthermore, a global control gate is introduced to co-tune the overall electrical characteristics, while active control of logic devices and extendable inputs are achieved based on this model. This work proposes a novel nanowire multi-gate configuration, which provides possibilities for localized, precise control of band structures and the fabrication of highly integrated, multifunctional, and controllable nano-devices.

π-Extended Rubrenes via Dearomative Annulative π-Extension Reaction.

Among a large variety of organic semiconducting materials, rubrene (5,6,11,12-tetraphenyltetracene) represents one of the most prominent molecular entities mainly because of its unusually high carrier mobility. Toward finding superior rubrene-based organic semiconductors, several synthetic strategies for related molecules have been established. However, despite its outstanding properties and significant attention in the field of materials science, late-stage functionalizations of rubrene remains undeveloped, thereby limiting the accessible chemical space of rubrene-based materials. Herein, we report on a late-stage π-extension of rubrene by dearomative annulative π-extension (DAPEX), leading to the generation of rubrene derivatives having an extended acene core. The Diels-Alder reaction of rubrene with 4-methyl-1,2,4-triazoline-3,5-dione occurred to give 1:1 and 1:2 cycloadducts which further underwent iron-catalyzed annulative diarylation. The thus-formed 1:1 and 1:2 adducts were subjected to radical-mediated oxidation and thermal cycloreversion to furnish one-side and two-side π-extended rubrenes, respectively. These π-extended rubrenes displayed a marked red shift in absorption and emission spectra, clearly showing that the acene π-system of rubrene was extended not only structurally but also electronically. The X-ray crystallographic analysis uncovered interesting packing modes of these π-extended rubrenes. Particularly, two-side π-extended rubrene adopts a brick-wall packing structure with largely overlapping two-dimensional face-to-face π-π interactions. Finally, organic field-effect transistor devices using two-side π-extended rubrene were fabricated, and their carrier mobilities were measured. The observed maximum hole mobility of 1.49 × 10-3 cm2V-1 s-1, which is a comparable value to that of the thin-film transistor using rubrene, clearly shows the potential utility of two-side π-extended rubrene in organic electronics.

Narrowed Si0.7Ge0.3 channel FinFET with subthreshold swing of 64 mV/Dec using cyclic self-limited oxidation and removal process

A narrowed Si0.7Ge0.3 channel fin field-effect transistor (FinFET) device is demonstrated in detail by using an accurate cyclic wet treatment process. The Si0.7Ge0.3 fin/per side of 0.63 nm in thickness can be accurately removed in each cycle by utilizing a self-limited oxidation with 40% HNO3 solution in 40 s and oxidation removal can be achieved with 1% HF solution in 10 s. As a result, after the dummy gate removal, the fin width of Si0.7Ge0.3 can be narrowed from 20 nm to 8 nm by utilizing 10 cycles of this wet treatment process. Compared with the conventional Si0.7Ge0.3 FinFET under a similar process, the narrowed Si0.7Ge0.3 channel FinFET can realize a strong gate control capability by using this newly developed wet treatment process, because its subthreshold slope can be reduced by 24%, improving from 87 mV/dec to 64 mV/dec.

Solution-Processed Isoindigo- and Thienoisoindigo-Based Donor-Acceptor-Donor π-Conjugated Small Molecules: Synthesis, Morphology, Molecular Packing, and Field-Effect Transistor Characterization.

Molecular design and precise control of thin-film morphology and crystallinity of solution-processed small molecules are important for enhancing charge transport mobility of organic field-effect transistors and gaining more insight into the structure-property relationship. Here, two donor-acceptor-donor (D-A-D) architecture small molecules TRA-IID-TRA and TRA-TIID-TRA comprising an electron-donating triarylamine (TRA) and two different electron-withdrawing cores, isoindigo (IID) and thienoisoindigo (TIID), respectively, were synthesized and characterized. Replacing the phenylene rings of central IID A with thiophene gives a TIID core, which reduces the optical band gap and upshifts the energy levels of frontier molecular orbitals. The single-crystal structures and grazing-incidence wide-angle X-ray scattering (GIWAXS) analysis revealed that TRA-TIID-TRA exhibits the relatively tighter π-π stacking packing with preferential edge-on orientation, larger coherence length, and higher crystallinity due to the noncovalent S···O/S···π intermolecular interactions. The distinctly oriented and connected ribbon-like TRA-TIID-TRA crystalline film by the solution-shearing process achieved a superior hole mobility of 0.89 cm2 V-1 s-1 in the organic field-effect transistor (OFET) device, which is at least five times higher than that (0.17 cm2 V-1 s-1) of TRA-IID-TRA with clear cracks. Eventually, rational modulation of fused core in the π-conjugated D-A-D small molecule provides a new understanding of structural design for enhancing the performance of solution-processed organic semiconductors.

Comparison of contact metals evaporated onto monolayer molybdenum disulfide

Understanding and improving the contact resistance of two-dimensional materials for the fabrication of next-generation devices is of vital importance to be able to fully utilize the new physics available in these materials. In this work, eight different contact metals (Ag, Au, Cr, Cu, In, Mo, Ni, and Ti) have been investigated using the same sample of monolayer MoS2. Through the fabrication and testing of multiple, identically sized field-effect transistor devices per contact metal, we compensate for large variability in electrical properties of as-grown chemical vapor deposition MoS2 and deduce the relative performance of each metal. The general trend of lower work function metals having lower contact resistance holds with In, Ag, and Ti performing the best of the metals tested. Our results are compatible with recent research suggesting that the contact resistance in undoped, monolayer MoS2 is dominated by a lateral junction resistance, and we provide context for how this manifests in device-to-device variation. Multiple orders of magnitude differences in contact resistance are observed between metals and can be explained by this lateral barrier operating in the thermionic-field emission regime.

Electrical regulation of interfacial thermal conductance of graphene/MoS2 heterojunction: Uncovering the role of electrons

The van der Waals heterojunction of graphene and MoS2 has drawn extensive research in recent years, since it combines the advantages of both materials. The thermal transport across the interface is an important issue in practical application, which has been seldom experimentally studied for graphene/MoS2 heterojunction. Previous work only focused on the phonon coupling without considering the role of interfacial electronics, which caused a deviation between experimental and theoretical results. Herein, we employed photo-thermal Raman technique to characterize the interfacial thermal conductance of graphene/MoS2 heterojunction and revealed a value of 93.2 ± 10.2 MW/m2K on average. This value is much larger than theoretical predictions. Using source-drain bias (VD) and gate voltage in a field effect transistor device, we achieved effect regulation of interfacial electron transport and corresponding thermal conductance in a range of 55.1 ± 5.8 to 304.2 ± 32.1 MW/m2K. At VD with different signs, we uncovered a possible thermal rectification at the interface. We owed the change of interfacial thermal conductance to electron-assisted phonon-coupling, when electron's transfer between graphene and MoS2 may results in the phonon density redistribution.

Molecular Engineering of Chalcogen-Embedded Anthanthrenes via peri-Selective C-H Activation: Fine-Tuning of Crystal Packing for Organic Field-Effect Transistors.

Disclosed herein is a RhCl3 -catalyzed peri-selective C-H/C-H oxidative homo-coupling of 1-substituted naphthalenes, which provides a highly efficient and streamlined approach to chalcogen-embedded anthanthrenes from readily available starting materials. Introducing O, S, and Se into the anthanthrene skeleton leads to gradually increased π-π stacking distances but significantly enhanced π-π overlaps with the growth of the hetero-atom radius. Moderate π-π distance, overlap area, and intermolecular S-S interactions endow S-embedded anthanthrene (PTT) with excellent 2D charge-transport properties. Moreover, the transformation of p-type to n-type S-embedded anthanthrenes is realized for the first time via the S-atom oxidation from PTT to PTT-O4. In organic field-effect transistor devices, PTT derivatives exhibit hole transport with mobilities up to 1.1 cm2 V-1 s-1 , while PTT-O4 shows electron transport with a mobility of 0.022 cm2 V-1 s-1 .

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe2 Semiconductor Devices.

Palladium diselenide (PdSe2), as an emerging two-dimensional (2D) layered material, is gaining growing attention in nanoelectronics and optoelectronics due to its thickness-dependent band gap, high carrier mobility, and good air stability. However, its asymmetric pentagon structure is inclined to breed defects. Herein, the intrinsic Se vacancy-induced trap states and their influence on the hopping transport in PdSe2 are systematically investigated. We provide direct evidence that Se vacancies exist in the fresh PdSe2 samples, which results in the localized trapping states inside the band gap. For the few-layer PdSe2, at 77 K, the trap density (Dit) near the midgap is about 2.2 × 1013 cm-2 eV-1, whereas at 295 K, the Dit value increases to ∼7.1 × 1013 cm-2 eV-1. By comparison, the multilayer PdSe2 shows nonobvious temperature-dependent trap behaviors with almost unchanged Dit values of ∼8.1 × 1012 cm-2 eV-1 at midgap in the temperature range between 77 and 295 K. Thus, trap states in the few-layer PdSe2 are more vulnerable to temperature effect. Transport measurements demonstrated that both few-layer and multilayer PdSe2 field-effect transistor (FET) devices show n-type dominant ambipolar behaviors. The electron mobility in the multilayer PdSe2 FET is nearly 15-fold higher than that in the few-layer PdSe2 FET at 315 K, probably owing to the decreased effective mass and suppression of charge impurity scattering in the thicker channel material. However, both FET devices exhibit variable-range hopping over a temperature range from 77 to 240 K and thermally activated hopping at temperatures above 240 K. The hopping transport mechanism is strongly associated with the Se vacancy-induced localized states with poor screening and strong potential fluctuations. This study reveals the important role of structural defects in tailoring and improving the charge transport properties of PdSe2.

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

Electrically controlled molecular fingerprint retrieval with van der Waals metasurface

Polaritons in two-dimensional van der Waals (vdW) materials possess extreme light confinement, which have emerged as a potential platform for next-generation biosensing and infrared spectroscopy. Here, we propose an ultra-thin and electric tunable graphene/hexagonal boron nitride/graphene metasurface for detecting molecular fingerprints over a broad spectrum. The vdW metasurface supports hybrid plasmon–phonon polariton resonance with high-quality factor (Q > 120) and electrically controlled broadband spectra tunability from 6.5 to 7 μm. After coating a thin layer of bio-molecular (e.g., CBP) on top of the metasurface, the molecular absorption signatures can be readout at multiple spectral points and, thus, achieve broadband fingerprint retrieval of bio-molecules. Additionally, our electric tunable metasurface works as an integrated graphene-based field-effect transistor device, without the need of multiple resonance generators such as angle-resolved or pixelated dielectric metasurfaces for broadband spectra scanning, thereby paving the way for highly sensitive, miniaturized, and electrically addressed biosensing and infrared spectroscopy.

Electron transfer characteristics of amino acid adsorption on epitaxial graphene FETs on SiC substrates

Clarifying the adsorption characteristics of biomolecules on graphene surfaces is critical for the development of field-effect transistor (FET)-based biosensors for detecting pH, DNA, proteins, and other biomarkers. Although there are many reports on biomolecule detection using graphene FETs, the detection mechanism has not yet been clarified. In this study, the adsorption behavior and electron transfer characteristics of 20 proteinogenic amino acids on graphene field-effect transistors are investigated. Large single-crystal graphene films were epitaxially grown on SiC substrates by a resist-free metal stencil mask lithography process then patterned by air plasma etching to form FET devices. Amino acids with different charge conditions (positive or negative charge) were introduced onto the epitaxial graphene surface in solution. The charge neutral points of the drain current vs gate voltage curves shifted in the negative gate voltage direction after the introduction of all amino acids, regardless of the type of amino acid and its charge condition. These amino acid adsorption characteristics agree well with previously reported protein adsorption characteristics on epitaxial graphene surfaces, indicating that the adsorption of proteins in the liquid phase occurs by electron doping to the graphene surface. These results indicate that non-specific protein binding always leads to electron doping of epitaxial graphene FETs.

Fermi level unpinning achievement and transport modification in Hf1-Yb O /Al2O3/GaSb laminated stacks by doping engineering

Fermi level pinning and interface instability have hindered the achievement of field-effect-transistors (FETs) with high performance. Interface passivation and doping engineering technology have become the main driving force to solve the issue. Herein, interface chemistry and transport characteristics determination of Hf1-xYbxOy/Al2O3/GaSb gate stacks have been achieved by passivation and doping process. X-ray photoelectron spectroscopy characterization and electrical measurements have demonstrated the existence of less intrinsic oxides and elemental Sb at Hf1-xYbxOy/Al2O3/GaSb interface with optimized doping content, as well as the minimum leakage current density of 2.23 × 10–5 A cm-2. The energy distribution of interface state based on conductance method has confirmed the achievement of the lowest interface state density of 1.98×1013 eV-1 cm-2, resulting in Fermi level unpinning. Carrier transport mechanisms of Hf1-xYbxOy/Al2O3/GaSb MOS capacitors as a function of temperature have been investigated systematically and some important electrical parameters have been extracted. Comprehensive analyses show that sputtering-derived Hf1-xYbxOy/Al2O3/GaSb (x = 0.32) gate stack has potential application in future GaSb-based metal-oxide-semiconductor field effect transistor (MOSFET) devices.

Impact of Externally Induced Local Mechanical Stress on Electrical Performance of Decananometer MOSFETs

Vertical, gigapascal-level mechanical stress (MS) is induced at different locations along the channel of 40-nm effective gate length planar CMOS field-effect transistor (FET) devices and electrical parameter variations are investigated. In both p-and n-channel devices, the threshold voltage, mobility, and ON-current are seen to change proportionally with the additional MS, while gate-induced drain-leakage current increases exponentially. A clear effect of the location of the applied force along the source–drain direction is observed on the transistor parameters. Simulations show that a mechanical load located closer to the FET source induces a stronger asymmetry between the source and drain stresses. This leads to asymmetric subband splitting/warping, which reduces the backscattering rate at the source, in line with theoretical predictions on the importance of the channel barrier near the source for current in quasi-ballistic transistors.

Electrical and optical properties of InSe with various interfaces

In this work, we investigated how the electrical and photoelectrical properties of InSe based devices depend on the interfaces made with standard materials such as SiO2, BN, and PMMA. The use of a BN layer is found to not only change the carrier type but also weaken the out-of-plane vibration of InSe. Field-effect transistor devices show a p-type behavior for InSe on SiO2, while for InSe on BN, the majority carriers are electrons. Moreover, due to the weakened electron–phonon interaction the electron mobility of InSe on BN is more than two magnitudes greater than its hole mobility on SiO2. A p–n junction diode is also demonstrated with InSe/SiO2 and InSe/BN with a rectification ratio as high as 102 and a photoresponsivity of 52 A/W, which can be enhanced to 103 and 1.6 × 104 A/W with a PMMA coverlayer. Our results may be useful for the design of high-performance van der Waals heterojunction photodetectors.

A MEMS Micro Force Sensor Based on A Laterally Movable Gate Field-Effect Transistor (LMGFET) with A Novel Decoupling Sandwich Structure

This paper presents the development of a novel micro force sensor based on a laterally movable gate field-effect transistor (LMGFET). A precise electrical model is proposed for the performance evaluation of small-scale LMGFET devices and exhibits improved accuracy in comparison with previous models. A novel sandwich structure consisting of a gold cross-axis decoupling gate array layer and two soft photoresistive SU-8 layers is utilized. With the proposed dual-differential sensing configuration, the output current of the LMGFET lateral operation under vertical interference is largely eliminated, and the relative output error of the proposed sensor decreases from 4.53% (traditional differential configuration) to 0.01%. A practicable fabrication process is also developed and simulated for the proposed sensor. The proposed LMGFET-based force sensor exhibits a sensitivity of 4.65 µA·nN−1, which is comparable with vertically movable gate field-effect transistor (VMGFET) devices, but has an improved nonlinearity of 0.78% and a larger measurement range of ±5.10 µN. These analyses provide a comprehensive design optimization of the electrical and structural parameters of LMGFET devices and demonstrate the proposed sensor’s excellent force-sensing potential for biomedical micromanipulation applications.

Exploring the Role of 2D-Graphdiyne as a Charge Carrier Layer in Field-Effect Transistors for Non-Covalent Biological Immobilization against Human Diseases.

Graphdiyne's (GDY's) outstanding features have made it a novel 2D nanomaterial and a great candidate for electronic gadgets and optoelectronic devices, and it has opened new opportunities for the development of highly sensitive electronic and optical detection methods as well. Here, we testified a non-covalent grafting strategy in which GDY serves as a charge carrier layer and a bioaffinity substrate to immobilize biological receptors on GDY-based field-effect transistor (FET) devices. Firm non-covalent anchoring of biological molecules via pyrene groups and electrostatic interactions in addition to preserved electrical properties of GDY endows it with features of an ultrasensitive and stable detection mechanism. With emerging new forms and extending the subtypes of the already existing fatal diseases, genetic and biological knowledge demands more details. In this regard, we constructed simple yet efficient platforms using GDY-based FET devices in order to detect different kinds of biological molecules that threaten human health. The resulted data showed that the proposed non-covalent bioaffinity assays in GDY-based FET devices could be considered reliable strategies for novel label-free biosensing platforms, which still reach a high on/off ratio of over 104. The limits of detection of the FET devices to detect DNA strands, the CA19-9 antigen, microRNA-155, the CA15-3 antigen, and the COVID-19 antigen were 0.2 aM, 0.04 pU mL-1, 0.11 aM, 0.043 pU mL-1, and 0.003 fg mL-1, respectively, in the linear ranges of 1 aM to 1 pM, 1 pU mL-1 to 0.1 μU mL-1, 1 aM to 1 pM, 1 pU mL-1 to 10 μU mL-1, and 1 fg mL-1 to 10 ng mL-1, respectively. Finally, the extraordinary performance of these label-free FET biosensors with low detection limits, high sensitivity and selectivity, capable of being miniaturized, and implantability for in vivo analysis makes them a great candidate in disease diagnostics and point-of-care testing.