Characteristics Of Field-effect Transistors Research Articles

Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors

Growth and characterization of nitrogen-polar AlGaN/AlN and demonstration of field effect transistor

This study proposes a nitrogen-polar (N-polar) Al x Ga1−x N/Al0.9Ga0.1N/AlN structure that can generate a large amount of two-dimensional electron gas to enhance the device development of samples. Additionally, we have analyzed the critical thickness of N-polar AlGaN/AlN based on the theoretical calculations of three different values of film thickness. The metalorganic vapor-phase epitaxy method is used to grow N-polar Al x Ga1−x N/Al0.9Ga0.1N/AlN on sapphire substrates. The substrates with a misorientation angle of 2° along the m-axis and a-axis directions are selected to determine the effect of the off-cut angle on sample flatness and current–voltage characteristics. Furthermore, we determine the effect of Al contents on N-polar Al x Ga1−x N/Al0.9Ga0.1N/AlN under the optimum growth conditions of the growth thickness of the top layer of AlGaN and sapphire substrate. The results indicate that the current throughput increases with a decrease in Al content. Lastly, we have fabricated the N-polar AlGaN/AlN heterostructure field effect transistor (FET) to demonstrate the static FET characteristics.

Pulsed gate voltage measurement for charge mobility extraction of organic transistors

The field-effect mobility of organic semiconductors is an important parameter that describes a physical characteristic of charge carriers and is extracted from the current–voltage characteristics of field-effect transistors. For the parameter to be consistent with its physical definition, charge transport in organic semiconductors should be in a steady state. However, charge transport in organic field-effect transistors is often in a non-steady state because of the occurrence of charge-carrier trapping and the Joule heating effect; therefore, careful attention is required for the extraction of the field-effect mobility in such cases. In this study, the effects of gate pulses on the transport characteristics of organic field-effect transistors are investigated. Consequently, an ideal sequence of gate pulses to minimize the effects of intermediate trap states and Joule-heating during extraction of the field-effect mobility of organic transistors is proposed. Finally, an equation that relates the field-effect mobility to the sequence of gate pulses is derived and experimentally validated. • Systematic study of the effects of pulsed-gate measurements on the device characteristics of organic field-effect transistors. • Analytical model to describe the relationship between the effective mobility and gate pulse characteristics. • Ideal sequence of gate pulses for the extraction of the field-effect mobility of organic semiconductors.

Artificial Neural Network-Based Modeling for Estimating the Effects of Various Random Fluctuations on DC/Analog/RF Characteristics of GAA Si Nanosheet FETs

Advanced field-effect transistors (FETs), such as gate-all-around (GAA) nanowire (NW) and nanosheet (NS) devices, have been highly scaled; therefore, they are critically affected even by a microscopic fluctuation. As the GAA NS device is considered a promising candidate beyond 5-nm technology, it is essential to analyze the effects of these fluctuations on dc and analog/radio frequency (RF) characteristics for future applications. In this article, we for the first time demonstrate that the machine learning (ML)-aided numerical device simulation approach can be used to model the effects of various fluctuations on the characteristics of GAA NS FETs (NSFETs). Among various fluctuations, we mainly focus on work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF). The independent and combined effects of these fluctuations on the characteristics of NSFETs are studied. Except for transfer and output characteristics, analog and RF parameters, such as gate capacitance, transconductance, cutoff frequency, 3-dB frequency, and transconductance efficiency, are analyzed in detail. The main aim of this work is to show the capability and generality of ML in modeling various electrical characteristics of the explored NSFETs. The results show that the ML-based technique is fast and efficient, which accelerates the overall process and gives engineering acceptable accurate results.

Molybdenum disulfide field-effect transistors with enhanced charge-injection by inserting ultrathin pentacene layer under source/drain electrodes

We report a method to improve charge-injection properties of molybdenum disulfide (MoS2)-based field-effect transistors (FETs) by introducing ultrathin pentacene film as the buffer layer under the source/drain electrodes. Compared with conventional devices with metal-only electrodes, the electrical characteristics of MoS2 FETs with the organic buffer layer exhibit a ten-fold enhancement in on-state current and a four-fold increase in field-effect mobility. These improvements are attributed to the introduction of organic buffer layer with hole-type that result in optimized contact properties. The Schottky barrier height is lowered by approximately 0.3 eV for the electron-injection in MoS2 FETs. Furthermore, electrons in metal and MoS2 could be effectively attracted to the surfaces by holes in pentacene film resulting in a tunnelling probability, which is responsible for the improved charge-injection. Current studies will be helpful in the development of high performance MoS2 optoelectrical devices.

Controlled p-Type Doping of MoS2 Monolayer by Copper Chloride.

Electronic devices based on two-dimensional (2D) MoS2 show great promise as future building blocks in electronic circuits due to their outstanding electrical, optical, and mechanical properties. Despite the high importance of doping of these 2D materials for designing field-effect transistors (FETs) and logic circuits, a simple and controllable doping methodology still needs to be developed in order to tailor their device properties. Here, we found a simple and effective chemical doping strategy for MoS2 monolayers using CuCl2 solution. The CuCl2 solution was simply spin-coated on MoS2 with different concentrations under ambient conditions for effectively p-doping the MoS2 monolayers. This was systematically analyzed using various spectroscopic measurements using Raman, photoluminescence, and X-ray photoelectron and electrical measurements by observing the change in transfer and output characteristics of MoS2 FETs before and after CuCl2 doping, showing effective p-type doping behaviors as observed through the shift of threshold voltages (Vth) and reducing the ON and OFF current level. Our results open the possibility of providing effective and simple doping strategies for 2D materials and other nanomaterials without causing any detrimental damage.

Comparative analysis of Schottky barriers for heterogeneous defect domains in monolayer WS2 field-effect transistors

A major bottleneck in the applications of two-dimensional transition metal dichalcogenides (TMDs) is the realization of ohmic contacts by overcoming the Schottky barrier (SB) at metal–semiconductor interfaces. Although the physical properties of point defects in TMDs are the key to determining the SB characteristics, the correlation between the defect types and SBs is yet to be systematically explored. Here, we investigated the SB characteristics depending on the S vacancy (SV) and W vacancy (WV) in hexagonal WS2 field-effect transistors (FETs). This was implemented by fabricating the SV and WV FETs in each domain on a single-flake monolayer. Compared to WV FET, the SV FET exhibited a 10 times higher doping concentration and 4 times higher Coulomb scattering coefficient (α) resulting in higher low-frequency noise. The comparative SB characteristics of both FETs were investigated by Arrhenius plot for the on-current at high temperatures. Below 360 K, the activation energies (Ea) of the SV and WV FETs exhibited different values of 0.071 and 0.115 eV, respectively, whereas those values are similar above 360 K because sufficient thermal energy allows for tunneling at SBs. These results help us understand the correlation between the defect type, doping level, and SB in TMD-based electronic devices.

Effects of bromination on anthryl-capped DPP-based semiconductor materials: Improved electrical characteristics of organic field-effect transistors

Diketopyrrolopyrrole (DPP), typically flanked with thiophene rings as π-spacers, has been regarded as a promising electron-acceptor unit for constructing donor-acceptor-donor (D-A-D) type small molecule organic semiconductors. Exploring the relationships between its conjugation structure and semiconducting property is of great importance for both molecular design and device fabrication of such DPP materials. Herein we describe the synthesis, self-assembly, and transistor characteristics of two novel N- and N′− 2-octyldodecylated DPP derivatives which were modified with native anthracene (An) and brominated anthracene (Br-An) at 5-, 5′-position of the flanked thiophenes, respectively, namely An-DPP and Br-An-DPP. Attributing to the self-assembly behaviors, they exhibit enormous difference in hole transport characteristics on interdigitated-electrode based organic field-effect transistor (OFET) devices even though there is only two atoms’ discrepancy in accordance with their molecular structures. The characterization of OFETs with interdigitated-electrodes based on Br-An-DPP reveals p-channel operation with highest field-effect mobility of 0.2 cm2·V−1·s−1, which is 107 times higher than that of An-DPP (4.8 × 10−8 cm2·V−1·s−1), and with a threshold voltage of - 2.5 V. X-ray diffraction, atomic force microscopy, scanning electron microscopy, and optical absorption studies reveal the presence of crystalline films caused by bromination on anthracene-modified alkylated DPP (i.e., Br-An-DPP), while An-DPP exhibits completely amorphous phase.

The Interfacial Properties of Monolayer MX–Metal Contacts

Binary IV–VI chalcogenides MXs (SnS, SnSe, SnTe, GeS, GeSe, and GeTe), as a family two-dimensional (2D) semiconductor material, have a proper bandgap, high carrier mobility, stability in ambient conditions, and a pucker structure, hence they are potential channel materials for the next-generation electronic and optoelectronic devices. 2D MXs devices should directly contact the metal electrodes to inject suitable types of carriers, on account of the random dopant fluctuation. However, a Schottky contact is always formed at the interface, which degrades the performance of the MXs devices. Herein, we report the contact characteristics of the MXs field-effect transistors (FETs) with Graphene(Gr)/Ag/Au electrodes (two-interface model) by using quantum transport calculations and density functional theory. At the vertical interface, the MXs FETs form Van der Waals (vdW) contact type after being contacted with the Gr electrode, and an Ohmic contact is formed after being contacted with Ag and Au electrodes. At the lateral interface, the SnTe (armchair and zigzag), GeS (zigzag), and GeSe (zigzag) FETs with Gr electrode get a desired p-type Ohmic contact or quasi p-type Ohmic contact, suggestive of high device performance in such an MXs device. Our simulation provides a theoretical foundation for the choice of suitable electrodes in future ML MXs devices.

Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor Characteristics

A simple, compact, and fundamental physics-based quasi-analytical model for single-layer graphene field effect transistors (GFETs) with large-area graphene is presented using a quantum mechanical density gradient method-based calculation. The device statistical physics of the two-dimensional (2D) graphene channel is studied analytically. This modelling leads to the precise drain current of the GFETs. The drain current calculation for the GFETs starts from charge carrier concentration, its density of states, and quantum capacitance (QC). QC depends primarily on the channel voltage, and is also a function of the gate-to-source voltage Vgs and drain-to-source voltage Vds. The formulation of the drain current with velocity saturation was carried out using the Monte Carlo simulation method. The performance of the analytical GFET model is characterized by the precise values of QC, its impact on drain current, and output characteristics. The impact of QC on FET devices at nanoscale is that it adds nonlinearity to the characteristic curves. The proposed method provides better QC results than the available analytical and simulated models.

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a 4◦ off-axis cut, N+ doped 4H-SiC substrate (the back gate) with, on top of, it a 1μm semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching.

Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III-V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe2) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe2 channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe2 FET are systematically monitored during this layer-by-layer recess-channel process. The WSe2 etching rate is estimated to be 2-3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WOX) layer grown through ultraviolet-ozone treatment induces robust p-doping in the neighboring (or underlying) WSe2 through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe2 FETs enables the realization of a high on/off output current ratio (>108) and field-effect mobility (∼190 cm2/V·s), while maintaining low contact resistance (0.9-6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.

Modulation of the electronic state of carbon thin films by inorganic substrates

The control of the electronic states of carbon-based materials is of great importance for the widespread use of carbon materials as electronic devices and catalysts. This article reports a novel method of controlling the electronic states of carbon-based materials by establishing covalent bonds between inorganic support materials and carbon thin films. Carbon thin films of 1 nm thickness were grown on inorganic substrates (Al2O3, AlN, and ZrO2) using chemical vapor deposition. Covalent bond formation was confirmed between the substrates and the carbon films. The investigations of field effect transistor characteristics and work function revealed the different relationships between the Dirac points and Fermi levels of carbon films depending on the type of substrate. The Fermi level of the films grown on Al2O3 or ZrO2 was found to be lower than the Dirac point energy level, with the ZrO2 sample exhibiting the lowest Fermi level. In contrast, the Fermi level of the film grown on AlN was located at a higher energy than the Dirac point. The Fermi level of the carbon film depends on the inorganic substrate, and the change in the Fermi level can be explained by the nature of the covalent bonds between the substrate and the film.

Simulation and Comparison of Current-Voltage Characteristics in Double Gate Nanowire FET Using ZnO and SiO2 as Gate Oxide Materials

The aim of the project is to simulate and compare current-voltage characteristics in double gate nanowire field effect transistors made of ZnO and SiO2 gate oxides with thicknesses ranging from 1 to 30 nm. Materials and methods: The drain characteristics of double gate nanowire FET for the two gate oxides were considered for analysis. Altogether 147 drain current samples were considered for each group. Results: The two groups are subjected to an independent sample test using SPSS software, which calculates the significant mean value. The SPSS tool's chart builder is used to create a statistical graph. The mean for those in the highest quartile of drain current of ZnO based DG NW FET (drain current=0.461 mA, 95% CI:0.232-0.458 mA, p<0.05), but in SiO2 based DG NW FET (drain current=0.115 mA, 95% CI:0.232-0.458 mA, p<0.05). Conclusion: ZnO nanowire field-effect transistors have better switching characteristics and higher drain current than SiO2. The drain current is altered by varying the oxide thickness of the material. The drain current of ZnO is significantly higher than that of SiO2.

Study on memory characteristics of fin-shaped feedback field effect transistor

The nonvolatile and volatile memory characteristics of feedback field-effect transistors (FBFETs) with nitride charge storage layers were theoretically studied. Because of the electrons and holes stored in the nitride layer, the threshold voltage (V TH) window of 0.6 V was opened/observed. And, with the help of the formation of a positive feedback loop in the p+–n+–p–n+ doped silicon region in FBFET, it turned out that the read delay time of the FBFET for nonvolatile memory applications can be shorter than 1 ns. On the other hand, for the volatile memory applications, the FBFET can implement (a) non-destructive read operations owing to the self-sustaining feedback loop characteristic, and (b) a significantly long retention time which can suppress the power dissipation in refresh. Furthermore, the operation scheme of volatile memory mode can be simplified by setting gate voltage conditions for the hold and read operations to be identical to each other. The FBFET showed its on-state drive current of 6 × 10−5 A μm−1 and the on-/off-current ratio of 109. The potential of merging nonvolatile and volatile memory devices in a single cell is discussed and demonstrated in this work.

Analysis of Schottky barrier heights and reduced Fermi-level pinning in monolayer CVD-grown MoS2 field-effect-transistors

Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS2) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoS2 field-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoS2 was utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoS2 FETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoS2 compared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky–Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.

Characterizations of Ion-Sensitive Field-Effect Transistors with Silicon Wire Array Channels and Stack-Sensing Membrane

In this study, the characteristics of ion-sensitive field-effect transistors (ISFETs) with silicon wire array channels and sensing membrane stacks of 3-aminopropyltriethoxysilane (APTES)/SiO2 were investigated. Si wires were fabricated by nanoimprint lithography and Si anisotropic/isotropic reactive-ion etching processes. The Si wires, with a line width of ∼200 nm, were undercut and nearly suspended, which formed an -shape cross-section. The aspects of wires were investigated using an optical microscope, an atomic force microscope, a scanning electron microscope, and a transmission electron microscope. The sensitivity, hysteresis, and drift of ISFETs were investigated. The above sensing properties were all significantly improved with the proposed channels and the sensing membrane stacks. As such, high-performance ISFETs can be realized for future biochemical applications.

Wet-Chemical Noncovalent Functionalization of CVD Graphene: Molecular Doping and Its Effect on Electrolyte-Gated Graphene Field-Effect Transistor Characteristics

Wet-Chemical Noncovalent Functionalization of CVD Graphene: Molecular Doping and Its Effect on Electrolyte-Gated Graphene Field-Effect Transistor Characteristics

Physics-Based DC Compact Modeling of Schottky Barrier and Reconfigurable Field-Effect Transistors

A closed-form and physics-based compact model is presented for calculating the DC characteristics of Schottky barrier field-effect transistors and dual gated reconfigurable field-effect transistors. The given model calculates the charge-carrier injection over the Schottky barriers. This current is separated into a field emission current, given by charge carriers tunneling through the Schottky barriers and a thermionic emission current, given by charge carriers overcoming the Schottky barriers. The model verification is done by comparing the model results to measurements and TCAD simulations.

Temperature-Dependent Electrical Characteristics of p-Channel Mode Feedback Field-Effect Transistors

In this study, the temperature-dependent electrical characteristics of p-channel mode feedback field-effect transistors (FBFETs) were examined at temperatures ranging from 250 to 425 K. Their steep subthreshold swings of less than 1 mV/dec were maintained even at temperatures up to 400 K. As the temperature increased to 400 K, the latch-up voltage shifted from -0.951 to -0.613 V, which was caused by a reduction in the potential barriers in the channels of the FBFETs. High Ion/Ioff ratios above 108 were maintained in the temperature range of 250 to 400 K. However, at temperatures over 400 K, the FBFETs were turned on regardless of the gate voltages owing to the generation of a thermally induced positive feedback loop.