Characteristics Of Field-effect Transistors Research Articles

Molecular beam epitaxial In2Te3 electronic devices

We report on the electrical characteristics of field-effect transistors (FETs) and Schottky diodes based on In2Te3 grown on hexagonal boron nitride (h-BN) substrates utilizing molecular beam epitaxy (MBE). A two-step growth method was used to increase surface coverage and large grain sizes for high-quality In2Te3. Scanning transmission electron microscopy (STEM) imaging revealed an atomically clean and abrupt interface between the In2Te3 and h-BN substrates. Compared with the previously reported In2Te3 FETs, the MBE-grown In2Te3 FETs exhibited superior electrical properties, including a mobility of 6.07 cm2 V−1 s−1, a subthreshold swing close to 6 V dec−1, and an impressive on/off ratio of approximately 105. Furthermore, the Ti/In2Te3 Schottky diodes exhibit a low saturation current of 0.4 nA, an ideality factor of 26.7, and a Schottky barrier height of 0.68 eV.

Photoinduced modulation and the effect of CNT loading on field effect transistor characteristics of CNT/ZnO/PVDF composite.

Carbon nanotube (CNT)/ZnO/ polyvinylidene fluoride (PVDF) polymer composite phototransistor is studied for the effect of CNT loading and the photoinduced modulation on its transfer characteristics. XRD study shows that the induced strain in the composite is due to the addition of CNT to the ZnO/PVDF composite. The percentage ofβ-phase present in PVDF is estimated through Raman spectroscopy and the composite's spectral response is determined by UV-Vis absorbance spectroscopy. From the DC electrical conductivity study it is found that the percolation threshold for the composites is obtained for 0.3 wt% of CNT, and 0.44 wt % of CNT loading makes the composite conductive. On adding 1 wt% of CNT, the electrical conductivity of the ZnO/PVDF composite increases 40 times (∼0.2μS m-1). The temperature-dependent DC conductivity shows that the conductivity of the composites changes from variable range hopping to band conductance upon an increase in CNT loading above the percolation threshold and exhibits a negative temperature coefficient. Two terminal photoconductivity studies are done to understand the photo enhancement and sensitivity of all the devices. PE hysteresis studies show that the polarization of the composites increases drastically from 0.05μC cm-2below the percolation threshold to 10-30μC cm-2above the percolation threshold of CNT in the composite. To study the effect of interfacial polarization on photoconductivity, the composite is studied in a three-terminal device format using SiO2as a gate dielectric. A band diagram analysis of the oxide-composite and CNT/ZnO interface is done to understand the mechanism behind the photoinduced field effect on transfer characteristics and the effect of CNT loading. The switching behavior and decay time under UV illumination are studied to understand the effect of CNT loading and photoinduced polarization. The persistent photoconductivity decreases and the charge collection efficiency of the FET increases as the CNT loading increases.

Strain-dependent charge trapping and its impact on the operational stability of polymer field-effect transistors

Despite recent dramatic improvements in the electronic characteristics of stretchable organic field-effect transistors (FETs), their low operational stability remains a bottleneck for their use in practical applications. Here, the operational stability, especially the bias-stress stability, of semiconducting polymer-based FETs under various tensile strains is investigated. Analyses on the structure of stretched semiconducting polymer films and spectroscopic quantification of trapped charges within them reveal the major cause of the strain-dependent bias-stress instability of the FETs. Devices with larger strains exhibit lower stability than those with smaller strains because of the increased water content, which is accompanied by the formation of cracks and nanoscale cavities in the semiconducting polymer film as results of the applied strain. The strain-dependence of bias-stress stability of stretchable OFETs can be eliminated by passivating the devices to avoid penetration of water molecules. This work provides new insights for the development of bias-stable stretchable OFETs.

Biosensing beyond Debye screening length using epitaxial graphene field-effect transistors on SiC substrate

We demonstrated the antigen detection beyond Debye screening length using antibody-modified epitaxial graphene field-effect transistors (FETs), which have been considered to be impossible because of the Debye screening length. The transfer characteristics of the graphene FETs with a single crystal epitaxial graphene film showed no concentration dependence of buffer solutions. The capacitance measurements in an epitaxial graphene FET also showed no concentration dependence, indicating that the solution-gate capacitance of the epitaxial graphene FET was independent on the Debye screening length. In addition, the minimum capacitance values were also almost independent for the concentration change. Since the Debye screening length depends on the ionic strength of the solution, which is proportional to the buffer solution concentration, the electrical characteristics of solution-gated epitaxial graphene FETs are almost independent on the Debye screening length owing to their small quantum capacitance. The antibody-modified epitaxial graphene FETs indeed detected the antigen, indicating that the epitaxial graphene FETs can detect the target beyond the Debye screening length without any complicated device fabrication processes and other desalted apparatuses.

Process Development of a Liquid-Gated Graphene Field-Effect Transistor Gas Sensor for Applications in Smart Agriculture

A compact, multi-channel ionic liquid-gated graphene field-effect transistor (FET) has been proposed and developed in our work for on-field continuous monitoring of nitrate nitrogen and other nitrogen fertilizers to achieve sustainable and efficient farming practices in agriculture. However, fabricating graphene FETs with easy filling of ionic liquids, minimal graphene defects, and high process yields remains challenging, given the sensitivity of these devices to processing conditions and environmental factors. In this work, two approaches for the fabrication of our graphene FETs were presented, evaluated, and compared for high yields and easy filling of ionic liquids. The process difficulties, major obstacles, and improvements are discussed herein in detail. Both devices, those fabricated using a 3 μm-thick CYTOP® layer for position restriction and volume control of the ionic liquid and those using a ~20 nm-thick photosensitive hydrophobic layer for the same purpose, exhibited typical FET characteristics and were applicable to various application environments. The research findings and experiences presented in this paper will provide important references to related societies for the design, fabrication, and application of liquid-gated graphene FETs.

200 mm Wafer Level Characterization at 2 K of Si/SiGe Field-Effect Transistors

Si/SiGe has proven to be an excellent spin qubit platform, but industrial production of large-scale spin-qubit chips is missing. We use field effect transistors (FETs) to monitor and develop the quality of the fabrication process on 200 mm wafers at 2 K using a cryogenic wafer prober (CWP). This mass-characterization technique provides statistics on device performance. We observe variations in drain off current and gate threshold voltage of 213 FETs. These variations are related to bias voltage conditions during CWP cooldown, which differ from qubit chip cooldown. To address this, a new FET structure with an additional top gate is introduced, effectively suppressing unintentional charge accumulations. This eliminates drain off currents and improves homogeneity of FET characteristics at 2 K. Our results highlight significant impact of bias conditions during qubit chip cooldown, which, if not accounted for in the qubit chip design, can lead to incorrect conclusions when using CWP.

An Internally Attached Aptameric Graphene Nanosensor for Sensitive Vasopressin Measurement in Critical Patient Monitoring.

This paper presents an aptameric graphene nanosensor for rapid and sensitive measurement of arginine vasopressin (AVP) toward continuous monitoring of critical care patients. The nanosensor is a field-effect transistor (FET) with monolayer graphene as the conducting channel and is functionalized with a new custom-designed aptamer for specific AVP recognition. Binding between the aptamer and AVP induces a change in the carrier density in the graphene and resulting in measurable changes in FET characteristics for determination of the AVP concentration. The aptamer, based on the natural enantiomer D-deoxyribose, possess optimized kinetic binding properties and is attached at an internal position to the graphene for enhanced sensitivity to low concentrations of AVP. Experimental results show that this aptameric graphene nanosensor is highly sensitive (with a limit of detection of 0.3 pM and a resolution of 0.1 pM) to AVP, and rapidly responsive (within 90 s) to both increasing and decreasing AVP concentration changes. The device is also reversable (within 4%), repeatable (within 4%) and reproducible (within 5%) in AVP measurements.

A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Abstract IIn this paper, two substrate optimization approaches of triple stacked Nanosheet FET (SNSHFET), namely optimization of buried oxide and selective deposition of punch through stopper (PTS) substrate, have been examined and simulations have been carried out using Technology Computer-Aided (TCAD) software. A comprehensive study of leakage current and key electrical characteristics (I¬ON, VT, SS, DIBL) have also been extracted based on variation in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. GIDL current also increases with increased doping of the source and drain. Also, the impact of ultra-thin body substrate in SNSHFET is studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in Inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed at the channel-drain and gate-substrate overlap region for understanding the physical insights of leakage current in the SNSHFET. This work also answers the dependency of GIDL current on the gate and drain voltage supply respectively. In addition to that, how GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. The 3 nm-based SNSHFET is designed and its electrical and GIDL characteristics are compared with novel devices like Forksheet FET and Complementary FET.

Enhancement of Synaptic Performance through Synergistic Indium Tungsten Oxide-Based Electric-Double-Layer and Electrochemical Doping Mechanisms

This study investigated the potential of indium tungsten oxide (IWO) channel-based inorganic electrolyte transistors as synaptic devices. We comparatively analyzed the electrical characteristics of indium gallium zinc oxide (IGZO) and IWO channels using phosphosilicate glass (PSG)-based electrolyte transistors, focusing on the effects of electric-double-layer (EDL) and electrochemical doping. The results showed the superior current retention characteristics of the IWO channel compared to the IGZO channel. To validate these findings, we compared the DC bias characteristics of SiO2-based field-effect transistors (FETs) with IGZO and IWO channels. Furthermore, by examining the transfer curve characteristics under various gate voltage (VG) sweep ranges for PSG transistors based on IGZO and IWO channels, we confirmed the reliability of the proposed mechanisms. Our results demonstrated the superior short-term plasticity of the IWO channel at VG = 1 V due to EDL operation, as confirmed by excitatory post-synaptic current measurements under pre-synaptic conditions. Additionally, we observed superior long-term plasticity at VG ≥ 2 V due to proton doping. Finally, the IWO channel-based FETs achieved a 92% recognition rate in pattern recognition simulations at VG = 4 V. IWO channel-based inorganic electrolyte transistors, therefore, have remarkable applicability in neuromorphic devices.

Performance improvement of planar silicon nanowire field effect transistors via catalyst atom doping control

Catalytic growth of silicon nanowires (SiNWs), mediated by metallic droplet, provide ideal quasi-1D channels to construct high performance field effect transistor (FET). However, the incorporation of catalytic metal atoms into SiNWs channels has significant impact on the FET characteristics, and thus needs to be better understood and controlled to fulfil its potential for high performance electronics. In this work, we focus on the effect of the incorporation of indium (In) catalytic atoms into planar SiNWs, grown via an in-plane solid-liquid-solid (IPSLS) mechanism, on the FET device performance. It is found that the initial high concentration of p-type In dopants in the as-grown SiNWs led to an equivalent boron (B) doping of 5×1018 cm−3. However, a simple step-wise annealing in oxygen at different temperatures, varied from 620 °C to 920 °C, can help to out-diffuse the dissolved In atoms into the surface SiO2 layer, and reduce the In concentrations down to <5×1017 cm−3, as verified by atom-probe tomography (APT) and four-point-probe measurements. This effective dopant control enables a remarkable device performance improvement of the Schottky barrier FETs, built upon an orderly array of parallel SiNWs of approximately 25 nm in diameter, where the current ratio (Ion/Ioff) has been substantially boosted from 105 to 108, while the subthreshold swing (SS) reduced from 400 mV/dec down to ∼100 mV/dec, with a hole carrier mobility increased from 10 to ∼75 cm2 V−1 s−1 as extracted according to a finite element analysis. These results pave the way for the employment of the catalytic IPSLS SiNWs to serve as high quality 1D channels for high-performance SiNWs-based electronics and sensors.

Fabrication of lateral diamond MOSFET with buried pn-junctions by diamond surface planarization based on carbon solid solution into nickel

New fabrication processes for buried p+-type diamond using etching techniques based on the solid-solution reaction of carbon with nickel were proposed and demonstrated. Specifically, an inversion-channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with source and drain regions buried in the body were fabricated, and their operation were confirmed. An etching process using etching techniques based on the solid-solution reaction of carbon with nickel was applied to realize trench formation and planarization after the growth of a p+-type diamond. The fabricated MOSFET exhibited drain current density equivalent to that of conventional MOSFET with source and drain p+-type regions deposited as islands on an n-type body, and ideal field-effect transistor characteristics with linear and saturation regions, and the drain current density was controlled by the gate voltage. However, the surface protrusion structure owing to the incomplete planarization process limited the device characteristics. The proposed fabrication processes for buried layers are expected to function as an important selective doping technique for diamond electronic devices such as ion implantation.

Reversible Polarity Control in 2D MoTe2 Field‐Effect Transistors for Complementary Logic Gate Applications

AbstractPrecise control over polarity in field‐effect transistors (FETs) plays a pivotal role in the design and construction of complementary metal–oxide–semiconductor (CMOS) logic circuits. In particular, achieving such precise polarity control in 2D semiconductors is crucial for the further development of advanced electronic applications beyond unit devices. This paper presents a systematic investigation on the reversible transition of carrier types in a 2D MoTe2 semiconductor under different annealing atmospheres. Photoemission spectroscopy and density functional theory (DFT) calculations demonstrate that annealing processes in vacuum and in ambient air induce a modification in the density of states, resulting in alterations in p‐type or n‐type characteristics. These reversible changes are attributed to the physisorption and elimination of oxygen on the surface of MoTe2. Furthermore, it is found that the device geometry affects the polarity of the transistor. By strategically manipulating both the annealing conditions and the geometric configuration, the n‐ and p‐type unipolar characteristics of MoTe2 FETs are successfully modulated and ultimately demonstrating that the functionality of not only a complementary inverter with a high voltage gain of ≈20, but also more complex logic circuits of NAND and NOR gates.

Reduced interface effect of proton beam irradiation on the electrical properties of WSe2/hBN field effect transistors

Two-dimensional transition metal dichalcogenide (TMDC) semiconductors are emerging as strong contenders for electronic devices that can be used in highly radioactive environments such as outer space where conventional silicon-based devices exhibit nonideal characteristics for such applications. To address the radiation-induced interface effects of TMDC-based electronic devices, we studied high-energy proton beam irradiation effects on the electrical properties of field-effect transistors (FETs) made with tungsten diselenide (WSe2) channels and hexagonal boron-nitride (hBN)/SiO2 gate dielectrics. The electrical characteristics of WSe2 FETs were measured before and after the irradiation at various proton beam doses of 1013, 1014, and 1015 cm−2. In particular, we demonstrated the dependence of proton irradiation-induced effects on hBN layer thickness in WSe2 FETs. We observed that the hBN layer reduces the WSe2/dielectric interface effect which would shift the transfer curve of the FET toward the positive direction of the gate voltage. Also, this interface effect was significantly suppressed when a thicker hBN layer was used. This phenomenon can be explained by the fact that the physical separation of the WSe2 channel and SiO2 dielectric by the hBN interlayer prevents the interface effects originating from the irradiation-induced positive trapped charges in SiO2 reaching the interface. This work will help improve our understanding of the interface effect of high-energy irradiation on TMDC-based nanoelectronic devices.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Polythiophene-based organic transistors：Time to a single nanowire and sub-5 nm gate length

Future organic field-effect transistors (FETs) may utilize one-dimensional (1D) semiconductor materials in their channels. In this study, we used the ab initio method to explore the transport characteristics of 1D nanowire polythiophene FETs comprehensively. Based on the 2028 map in the International Technology Roadmap for Semiconductors (ITRS) in 2013, our theoretical simulations showed that n-type and p-type gate-all-around (GAA) 1D polythiophene FETs with 5-nm gate length (Lg) and appropriate underlap (UL) satisfy the basic high-performance and low-power-consumption device applications. Moreover, both the n-type and p-type GAA 1D polythiophenee FETs (Lg = 3 nm) meet the high-performance needs of ITRS. Our numerical results revealed that the organic transistors can be designed by using a single nanowire and the minimum Lg of transistors can scale to 3 nm.

One-Dimensional MoS2 Nanoscrolls as Miniaturized Memories.

Dimensionality of materials is closely related to their physical properties. For two-dimensional (2D) semiconductors such as monolayer molybdenum disulfide (MoS2), converting them from 2D nanosheets to one-dimensional (1D) nanoscrolls could contribute to remarkable electronic and optoelectronic properties, yet the rolling-up process still lacks sufficient controllability, which limits the development of their device applications. Herein we report a modified solvent evaporation-induced rolling process that halts at intermediate states and achieve MoS2 nanoscrolls with high yield and decent axial uniformity. The accordingly fabricated nanoscroll memories exhibit an on/off ratio of ∼104 and a retention time exceeding 103 s and can realize multilevel storage with pulsed gate voltages. Such open-end, high-curvature, and hollow 1D nanostructures provide new possibilities to manipulate the hysteresis windows and, consequently, the charge storage characteristics of nanoscale field-effect transistors, thereby holding great promise for the development of miniaturized memories.

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

In this study, we applied ferroelectrics to the gate stack of Field Effect Transistors (FETs) with a 2D transition-metal dichalcogenide (TMDC) channel, actively researching for sub-2nm technology node implementation. Subsequently, we analyzed the circuit characteristics of Logic-in-Memory (LiM) operation and utilized LiM features after applying ferroelectrics to achieve a single-device configuration. Based on well-calibrated simulations, we performed compact modeling in a circuit simulator to depict the temperature-dependent electrical characteristics of ferroelectric FETs with a double gate structure and 2D channel (DG 2D-FeFET) in sub-2nm dimensions. Through this, we have confirmed that the 2D FeFET-based LiM technology, designed for the 2 nm technology node, exhibits superior characteristics in terms of delay, power/energy consumption, and circuit area under all temperature conditions, compared to the conventional CMOS technology based on 2D FETs. This verification serves as proof of the future technological potential of 2D-FeFET in extremely scaled-down technology nodes.

Non-volatile memory characteristics of flexible ferroelectric field-effect transistors consisting of Sm-doped BiFeO3 thin films

This study investigates the impact of Sm doping on the structural, electrical, and functional properties of BiFeO3 (BFO) thin films. The aim is to improve their non-volatile memory characteristics for use in flexible ferroelectric field-effect transistors (FeFETs). We fabricated Sm-doped BFO (SBFO) thin films on flexible mica substrates with Sm concentrations ranging from 0 to 15 %. The FeFET device structures, which include MoS2 monolayer channels and SBFO thin films with Pt bottom electrodes, were analyzed. The SBFO thin films displayed a (111) preferential orientation due to the influence of underlying Pt electrodes. Notably, the SBFO thin film doped with a 10 % Sm concentration showed optimal enhancements, including a reduction in leakage current density and an increase in remanent polarization to 55.8 μC/cm2, compared to undoped thin film (35.5 μC/cm2). Furthermore, the thin film exhibited superior fatigue resistance for up to 1012 switching cycles and maintained stable values under significant bending stress for ferroelectric polarizations. On the other hand, SBFO thin film with 15 % Sm doping displayed relaxor antiferroelectric behavior, highlighting the importance of doping concentration. Therefore, for non-volatile memory application reliability, the FeFET device featuring a 10 % Sm-doped SBFO thin film not only enhanced the memory window but also showed superior fatigue characteristics over 1012 switching cycles, compared to its undoped counterpart. These findings demonstrate the effect of Sm doping in customizing the properties of BFO thin films for advanced, flexible non-volatile memory devices, offering a novel insight to optimize ferroelectric field-effect transistor performance.

Understanding Quasi-Static and Dynamic Characteristics of Organic Ferroelectric Field Effect Transistors.

Leveraging poly(vinylidene fluoride-trifluoroethylene) [(PVDF-TrFE)] as the dielectric, we fabricated organic ferroelectric field-effect transistors (OFe-FETs). These devices demonstrate quasi-static transfer characteristics that include a hysteresis window alongside transient phenomena that bear resemblance to synaptic plasticity-encapsulating excitatory postsynaptic current (EPSC) as well as both short-term and long-term potentiation (STP/LTP). We also explore and elucidate other aspects such as the subthreshold swing and the hysteresis window under dynamic state by varying the pace of voltage sweeps. In addition, we developed an analytical model that describes the electrical properties of OFe-FETs, which melds an empirical formula for ferroelectric polarization with a compact model. This model agrees well with the experimental data concerning quasi-static transfer characteristics, potentially serving as a quantitative tool to improve the understanding and design of OFe-FETs.

Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of -200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from -1.01 V (1.34 V) to -11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to -200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.