Field Acceleration Factor Research Articles

An analog to digital converter in a SiC CMOS technology for high-temperature applications

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.

Comparison of Cobalt Integration with Various Dielectric Materials under Thermal and Electrical Stress

Cobalt (Co) is proposed to replace copper (Cu) as a conductor in the back-end-of-line (BEOL) interconnects of integrated circuits. In this study, the electric characteristics and reliability of the integration of Co with various dielectric films (SiO2, dense, and porous low-k SiOCH films) under thermal and electrical stress were compared. Thermal annealing repaired sputtering-Co-deposition-induced damage to the dielectric film but reduced the breakdown field and time-dependence-dielectric-breakdown (TDDB) times due to the diffusion of Co atoms. After annealing, the SiO2 film had the largest reductions in the breakdown field, TDDB failure time, and electric field acceleration factor, indicating that the diffusion of Co atoms dominates in the oxygen-rich surface. Under electrical stress, the drift of Co atoms favors the porous low-k film with the assistance of porosity. As a result, a barrier is required for Co metallization. To achieve barrier-free or barrier-less processing in Co metallization, the dense low-k film is the best option to integrate with Co.

Reliability Characteristics of Metal-Insulator-Semiconductor Capacitors with Low-Dielectric-Constant Materials.

In this study, the reliability characteristics of metal-insulator-semiconductor (MIS) capacitor structures with low-dielectric-constant (low-k) materials have been investigated in terms of metal gate area and geometry and thickness of dielectric film effects. Two low-k materials, dense and porous low-k films, were used. Experimental results indicated that the porous low-k films had shorter breakdown times, lower Weibull slope parameters and electric field acceleration factors, and weaker thickness-dependence breakdowns compared to the dense low-k films. Additionally, a larger derivation in dielectric breakdown projection model and a single Weilbull plot of the breakdown time distributions from various areas merging was observed. This study also pointed out that the porous low-k film in the irregular-shaped metal gate MIS capacitor had a larger dielectric breakdown time than that in the square- and circle-shaped samples, which violates the trend of the sustained electric field. As a result, another breakdown mechanism exists in the irregular-shaped sample, which is required to explore in the future work.

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO2 layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium- and long-term time-dependent dielectric breakdowns (TDDBs) of 65-nm-thick SiO2 layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler–Nordheim (F-N) tunneling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is the highest known for native SiO2 layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests that the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified and confirmed by both medium- and long-term results. Although two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (>8.5 MV/cm) should be attributed to the electron impact ionization within SiO2. At room temperature, the field acceleration factor is found to be $\approx 0.906$ dec/(MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm.

Approaching Ultimate Intrinsic SNR in a Uniform Spherical Sample with Finite Arrays of Loop Coils.

We investigated to what degree and at what rate the ultimate intrinsic (UI) signal-to-noise ratio (SNR) may be approached using finite radiofrequency detector arrays. We used full-wave electromagnetic field simulations based on dyadic Green's functions to compare the SNR of arrays of loops surrounding a uniform sphere with the ultimate intrinsic SNR (UISNR), for increasing numbers of elements over a range of magnetic field strengths, voxel positions, sphere sizes, and acceleration factors. We evaluated the effect of coil conductor losses and the performance of a variety of distinct geometrical arrangements such as "helmet" and "open-pole" configurations in multiple imaging planes. Our results indicate that UISNR at the center is rapidly approached with encircling arrays and performance is substantially lower near the surface, where a quadrature detection configuration tailored to voxel position is optimal. Coil noise is negligible at high field, where sample noise dominates. Central SNR for practical array configurations such as the helmet is similar to that of close-packed arrangements. The observed trends can provide physical insights to improve coil design.

TDDB characteristic and breakdown mechanism of ultra-thin SiO2/HfO2 bilayer gate dielectrics

The characteristics of TDDB (time-dependent dielectric breakdown) and SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT (equivalent-oxide-thickness) of the gate stack (Si/SiO2/HfO2/TiN/TiAl/TiN/W) is 0.91 nm. The field acceleration factor extracted in TDDB experiments is 1.59 s·cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 °C for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the breakdown behavior. The trap energy levels can be calculated by the SILC peaks: one SILC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Furthermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.

Identifying the First Layer to Fail in Dual-Layer ${\rm SiO}_{\rm x}/{\rm HfSiON}$ Gate Dielectric Stacks

We use the thermo-chemical model of bond breakage to investigate the degradation occurring in dual-layer SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfSiON gate dielectric stacks during low-compliance soft breakdown (BD) experiments, with the ultimate goal of identifying the first layer that degrades. Time-dependent dielectric breakdown experiments reveal that the degradation of conventional SiON and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfSiON dielectric stacks have the same kinetics, i.e., activation energy and field acceleration factor. This finding, supported by physics-based BD simulations, shows that the degradation in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HFSiON stacks is governed by the defect generation in the silicon oxide interfacial layer, which is the first that degrades in the multilayer stack.

Failure Rates for Interconnect Dielectric Breakdown: Trends Determining Technology Reliability Scaling Limits

In this paper, the dielectric properties [dielectric constant κ and thickness d (in nanometers)] that are necessary for the reliable operation of interline dielectrics used for passivation of copper interconnects in integrated circuits are determined. By relating the field acceleration factor to the dielectric constant, the optimum dielectric properties needed for meeting industrial reliability targets are estimated. This fundamental analysis offers a method of rationally introducing new materials to meet technology performance goals while maintaining reliability targets.

Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms.

Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliability of oxide at high temperatures are necessary. In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field-effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C and stress electric fields between 6 and 10 MV/cm. The field-acceleration factor is around 1.5 dec/(MV/cm) for all of the temperatures. The thermal activation energy is found to be ~ 0.9 eV, independent of the electric field. The area dependence of Weibull slope is discussed and shown to be a possible indication that the oxide quality has not reached the intrinsic regime and further oxide-reliability improvements are possible. Since our reliability data contradict the widely accepted belief that silicon oxide on SiC is fundamentally limited by its smaller conduction-band offset compared with Si, a detailed discussion is provided to examine the arguments of the early predictions.

Gate Oxide Long-Term Reliability of 4H-SiC MOS Devices

Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Filamentary model of dielectric breakdown

A dielectric breakdown model based on the phenomenological description of the nucleation and growth of filaments is proposed. This description involves different characteristic times according to the interfacial or bulk nature of the growth processes. The resulting time to breakdown distribution presents Weibull or bimodal shape according to the relative values of those characteristic times. In particular, the variation in the Weibull slope with thickness is observable when the interfacial process characteristic time is the larger. Bimodal shapes are observable when the characteristics times are in the same range and the surface scaling of the distributions influences the apparent Weibull slopes. The model is compared to experimental constant voltage stress and linear ramp voltage stress measurements made on metal insulator metal and metal oxide semiconductors structures. The physical parameters extracted are discussed. Breakdown electric fields are derived as functions of temperature, dielectric thickness, and dielectric permittivity consistently with experimental trends. The electric field acceleration factors are also derived and depend on dielectric thickness.

Dominant Factors in TDDB Degradation of Cu Interconnects

The field acceleration factor (/spl gamma/) for the E-model of time-dependent dielectric breakdown (TDDB) in various Cu interconnect structures has been studied. The /spl gamma/ for pSiCN structures is larger than that of pSiN structures and independent of the kind of interlayer dielectric material or other processes used to make it. The relationship between the breakdown electric field strength (E/sub BD/) and the TDDB lifetime has been investigated. It has been demonstrated that the TDDB lifetime can be predicted from experimentally measured E/sub BD/ and /spl gamma/. An E/sub BD/ of at least 4.2 MV/cm is necessary to assure ten-year reliability under 0.2 MV/cm operation. Moreover, the important factors influencing the TDDB lifetime for Cu interconnects have been discussed. These include the Cu chemical-mechanical polishing (CMP), the post-CMP annealing, line edge roughness, and fine line effect.

An analytical expression for predicting wearout lifetime of thin gate and tunneling oxide

In this paper, a physical model is presented for estimating the mean intrinsic breakdown time of SiO 2. Using a general compensation law and assuming that the current–voltage characteristic is dominated by modified Mott–Gurney hopping prior to breakdown, a simple analytical expression for predicting the mean intrinsic breakdown wearout lifetime of oxides can be obtained. The analytical results describe well the following features of the data, (1) a thermal acceleration factor which is a linear function of the stressing electric field and (2) a field acceleration factor that is proportional to reciprocal temperature. The existing closed form expression gives a good fit to experimentally obtained mean intrinsic breakdown time of oxides in the literature.

Time-dependent-dielectric-breakdown of hydrogen implanted polyoxides

The time-to-breakdown (tbd) of polysilicon/polyoxide/polysilicon structures, hydrogenated by hydrogen ion implantation, is investigated. The ln(tbd) versus 1/Eox projection lines are corrected by using an average oxide field enhancement factor for the interface polysilicon/thermally grown polyoxide. A field acceleration factor G≈270MV/cm in the time-to-breakdown projection line is obtained. The obtained lower values of the field acceleration factor G, in comparison to as-grown polyoxides, are explained in the terms of the oxide traps generated during the hydrogen ion implantation.

Oxide field enhancement corrected time dependent dielectric breakdown of polyoxides

Time-to-breakdown (tbd) of polysilicon/polyoxide/polysilicon structures is investigated on small and large area capacitors. The ln(tbd) versus 1/Eox projection lines are corrected by using an average oxide field enhancement factor for the interface polysilicon/thermally grown polyoxide. A field acceleration factor G≈320MV/cm in the time-to-breakdown projection line is obtained. It is shown that the fast prediction of time-to-breakdown can be achieved with short stress time measurements in structures of different area.

Investigation of the intrinsic SiO 2 area dependence using TDDB testing and model integration into the design process

This paper models the area dependency for thin SiO 2 films (1.2E-7 to lE-2 cm 2) using Time Dependent Dielectric Breakdown testing over a wide range of electric fields and test temperatures. The data generated indicates that the field and temperature acceleration factors are the same for all the areas tested indicating that the failure mechanism is the same even though the times to failure are different for all the area sizes. The paper will explain and model the area effect on TDDB lifetime and use the model to predict gate oxide reliability in the design cycle.

Breakdown characteristics of ultra thin gate oxides following field and temperature stresses

Here, we investigate the reliability of silicon dioxide layers for two different thickness values (8 and 4.5 nm). The time to breakdown ( t bd) was determined using constant voltage stress (CVS) under different experimental conditions. The first set of data, which was used to determine the activation energy, corresponds to t bd at fixed electric field and different temperatures. The second set of data was obtained at fixed temperature and increasing electric field and was used to determine the field acceleration factor. It is shown that both activation energy and field acceleration factor can be used to determine the lifetime and the reliability of the gate oxide. For the thinner oxide, we observed a different behavior. In fact, during the CVS of the 4.5 nm thick oxide a quasi-breakdown phenomenon was found. The light emission which occurred during this phenomenon was investigated.

Top‐Oxidation Effects on the Reliability of Oxide‐Nitride‐Oxide Stacked Film

Effects of top‐oxidation on the reliability of oxide/nitride/oxide (ONO) stacked films have been investigated for different oxidation methods. The leakage current electric field acceleration factor (β) of mean time to failure, and reliability of ONO stacked films are strongly affected by the top‐oxide thickness and the oxidation methods. The optimum top‐oxide thickness on the nitride film is 2 to 3 nm. Leakage current and β are improved by dry/TCA (1,1,1‐trichloroethane) top‐oxidation instead of dry oxidation. By using dry/TCA top‐oxidation, high β, low leakage current, low defect density, and highly reliable ONO stacked films can be obtained.