Ferroelectric Insulator Research Articles

Structural and electrical properties of Al/BiFeO3/ZrO2/n-Si structure for non-volatile memory application

In this communication, the structural and electrical properties of metal–ferroelectric–insulator–silicon (MFIS) capacitor structure have been reported for non-volatile memory applications. Sol–gel with spin coating and rf sputtering process have been used for depositing BiFeO3 (BFO) and ZrO2 films, respectively. It has been observed that BFO film shows pure ferroelectric phase, uniform grain size and maximum refractive index at annealing temperature of 500 °C. Thermo-gravimetric analyzer and differential scanning calorimetry analysis indicate good agreement with X-ray diffraction of BFO film. In ZrO2 thin film, it has been observed that ZrO2 is in amorphous state at all annealing temperatures and the maximum refractive index has been found at annealing temperature of 400 °C. Al/ZrO2/n-Si (MIS), Al/BiFeO3/n-Si (MFS) and Al/BiFeO3/ZrO2/n-Si (MFIS) structures have been fabricated to investigate the electrical characteristics. The memory window has been observed by capacitance–voltage (C–V) characteristics and it improves from 1.9 V in MFS structure to 5.4 V in MFIS structure with 8 nm dielectric layer. Leakage current density has been observed by current density–gate voltage (J–V) characteristics and it is order of 10−5 A/cm2 in MF150 nmI8 nmS structure. No charge value degrades up to 1012 iteration cycles in MF150 nmI8 nmS structure.

Unveiling the Apparent “Negative Capacitance” Effects Resulting From Pulse Measurements of Ferroelectric-Dielectric Bilayer Capacitors

Apparent `Negative Capacitance' (NC) effects have been observed in some ferroelectric-dielectric (FE-DE) bilayers by pulse measurements, and the associated results have been published that claim to be direct evidence to support the quasi-static `negative capacitance' (QSNC) idea. However, the `NC' effects only occur when sufficiently high voltage is applied, and even exist in stand-alone FE capacitors. These results contradict the QSNC theory, as it predicts that once stabilized (requires a DE layer), the FE remains in the `NC' state regardless of the applied voltage. In this letter, by the use of Nucleation-Limited-Switching (NLS) model, we present our results obtained from simulation of pulse measurements on samples that are similar to the published ones. The simulation results indicate that reverse polarization switching occurs upon the falling edge of the pulses, which leads to the apparent hysteresis-free NC effect. This work provides an alternative interpretation of the experimental results without invoking the QSNC theory.

Lanthanum-doped BiFeO3/ZrO2 gate stack for ferroelectric field effect transistors

A metal–ferroelectric–insulator–semiconductor (MFIS) structure was fabricated with lanthanum (La)-doped BiFeO3 as ferroelectric and ZrO2 as the high-k insulator layer. The BiFeO3 film with 5 M doped La was prepared with sol–gel and ZrO2 film was physically deposited with rf sputtering. Films structural characteristics were obtained using X-ray diffraction and scanning electron microscopy (SEM). The ferroelectric film shows the perovskite structure with orientation (110)/(104) when annealed in the range from 400 to 700 °C. The dielectric film shows an amorphous structure for the same range of annealing temperature. Electrical and ferroelectric properties were obtained by fabricating and characterizing metal/ferroelectric/silicon (MFS), metal/ferroelectric/metal (MFM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/metal (MFIM) and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures with ferroelectric film of 200 nm thickness and dielectric film of various thicknesses. MFS structure shows a maximum memory window of 3.5 V and leakage current density of 1.4 × 10–8 A/cm2 with ferroelectric film annealed at 500 °C. The memory window was further improved to 6.62 V and leakage current to the order 10–10 A/cm2 with the introduction of 9 nm insulator layer between ferroelectric and silicon. The same device shows an excellent endurance property tested for 1012 cycles and data retention tested for 5.56 h. The device shows a breakdown of 43 V, which is 9 V higher than the MFS structure. To the best of author’s knowledge, this is the first report to integrate La-doped BiFeO3 on ZrO2 (high-k) dielectric for non-volatile memory applications.

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

RF Performance Projections of Negative-Capacitance FETs: fT , f max, and gmfT/ID

As continuous development and optimization of negative-capacitance field-effect transistors (NCFETs) are pursued for digital applications, it is also desirable to examine the radio frequency (RF) performance of these devices, especially devices with the metal-ferroelectric- insulator-semiconductor (MFIS) structure. In this article, we use a combination of physics-based modeling and small-signal circuits to investigate the RF performance of MFIS NCFETs using three key device figures of merit: the well-known unity-current-gain (cutoff) frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and the well-known maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , and another important metric specified by g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , where g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> is the transconductance and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> is the dc drain current. We find that MFIS NCFETs achieve similar f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> performance to conventional MOSFETs, but offer a significant advantage in g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> .

A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction

A novel metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node. Using 3-D TCAD simulations, we have varied the gate to source/drain junction overlap length, which shows that increased junction overlap offers reduced gate-induced drain leakage (GIDL) in NC-FinFET. We then show that the proposed JAM NC-FinFET provides superior ON -state current ( ${I}_{\text{ON}}$ ) to OFF -state current ( ${I}_{\text{OFF}}$ ) ratio with and without the self-heating effect (SHE). It also gives stable peak transconductance ( ${g}_{\text {m}}$ ) with and without SHE consideration due to reduced lattice temperature ( ${T}_{\text {I}} = 321$ K). A better capacitance matching due to the presence of depletion capacitance ( ${C}_{\text {dep}}$ ) is also observed, thereby resulting in low-hysteresis NC-FinFET design. The impact of gate metal work function variation on the hysteresis behavior of NC and JAM-NC-FinFET is also reported in this article. Furthermore, we show that the proposed JAM-NC-FinFET offers superior transconductance generation factor (TGF) in comparison with conventional NC-FinFET in the subthreshold region, making it a potential candidate for low-power applications.

Magnonic Magnetoelectric Coupling in Ferroelectric/Ferromagnetic Composites

Composite materials consisting of coupled magnetic and ferroelectric layers hold the promise for new emergent properties such as controlling magnetism with electric fields. Obviously, the interfacial coupling mechanism plays a crucial role and its understanding is the key for exploiting this material class for technological applications. This short review is focused on the magnonic‐based magnetoelectric coupling that forms at the interface of a metallic ferromagnet with a ferroelectric insulator. After analyzing the physics behind this coupling, the implication for the magnetic, transport, and optical properties of these composite materials is discussed. Furthermore, examples for the functionality of such interfaces are illustrated by the electric field controlled transport through ferroelectric/ferromagnetic tunnel junctions, the electrically and magnetically controlled optical properties, and the generation of electromagnon solitons for the use as reliable information carriers.

Impact of HfO2 buffer layer on the electrical characteristics of ferroelectric/high-k gate stack for nonvolatile memory applications

For the proposed work, the electrical properties of metal–ferroelectric–insulator–silicon (MFeIS) capacitors with Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric film deposited on HfO2/Si substrate have been investigated. The SBT film was deposited by RF sputtering and HfO2 film by plasma-enhanced atomic layer deposition (PEALD). The structural characteristic of the deposited ferroelectric and dielectric films was obtained using X-ray diffraction and multiple angle ellipsometric analysis. XRD results indicate the polycrystalline and perovskite structure of the SBT film and amorphous structure of the HfO2 film annealed at different temperatures. SBT film deposited on the silicon substrate and annealed at 500 °C shows the maximum refractive index of 3.46 with the maximum grain size of 32 nm. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS) and metal/ferroelectric/insulator/silicon (MFeIS) structures were fabricated to obtain the electrical and ferroelectric properties. MFeIS structure with 10 nm buffer layer shows the improved memory window of 5 V as compared to the 3.07 V in the MFeS structures. MFeI(10 nm)S structure even shows endurance higher than 1012 read/write cycles and data retention for more than 8 h.

Tuning Charge Transport in PVDF-Based Organic Ferroelectric Transistors: Status and Outlook.

The use of polymer ferroelectric dielectrics in organic field-effect transistors (FETs) for nonvolatile memory application was demonstrated more than 15 years ago. The ferroelectric dielectric polyvinylidene fluoride (PVDF) and its copolymers are most widely used for such applications. In addition to memory applications, polymer ferroelectrics as a dielectric layer in organic FETs yield insights into interfacial transport properties. Advantages of polymer ferroelectric dielectrics are their high dielectric constant compared to other polymer dielectrics and their tunable dielectric constant with temperature. Further, the polarization strength may also be tuned by externally poling the ferroelectric dielectric layer. Thus, PVDF and its copolymers provide a unique testbed not just for investigating polarization induced transport in organic FETs, but also enhancing device performance. This article discusses recent developments of PVDF-based ferroelectric organic FETs and capacitors with a focus on tuning transport properties. It is shown that FET carrier mobilities exhibit a weak temperature dependence as long as the dielectric is in the ferroelectric phase, which is attributed to a polarization fluctuation driven process. The low carrier mobilities in PVDF-based FETs can be enhanced by tuning the poling condition of the dielectric. In particular, by using solution-processed small molecule semiconductors and other donor-acceptor copolymers, it is shown that selective poling of the PVDF-based dielectric layer dramatically improves FET properties. Finally, the prospects of further improvement in organic ferroelectric FETs and their challenges are provided.

Novel Type of Synaptic Transistors Based on a Ferroelectric Semiconductor Channel.

Three-terminal synaptic transistors are basic units of neuromorphic computing chips, which may overcome the bottleneck of conventional von Neumann computing. So far, most of the three-terminal synaptic transistors use the dielectric layer to change the state of the channel and mimic the synaptic behavior. For this purpose, special dielectric layers are needed, such as ionic liquids, solid electrolytes, or ferroelectric insulators, which are difficult for miniaturization and integration. Here, we report a novel type of synaptic transistors using a two-dimensional ferroelectric semiconductor, i.e., α-In2Se3, as the channel material to mimic the synaptic behavior for the first time. The essential synaptic behaviors, such as single-spike response, paired-spike response, and multispike response have been experimentally demonstrated. Most importantly, the conventional gate dielectric material of our transistors may facilitate the miniaturization and batch manufacture of synaptic transistors. The results indicate that the three-terminal synaptic transistors based on two-dimensional ferroelectric semiconductors are very promising for neuromorphic systems.

Enhanced energy storage performance in a PVDF/PMMA/TiO2 blending nanodielectric material

The growing demand for miniaturization of electrical and electronic system poses a great challenge on energy storage capacitors, which requires associated dielectric materials exhibiting high energy density. In ferroelectric polymer dielectrics, it is one of the key issues to achieve both high dielectric permittivity and high breakdown strength. In this paper, we propose a method on improving the dielectric permittivity and breakdown strength concurrently taking the advantage of nanocomposite and blending. Our results show that PVDF/PMMA/TiO2 blending nanodielectric material presents improved relative dielectric permittivity of 12 and breakdown strength of 387 kV/mm compared with pristine PVDF, leading to an enhanced energy density about 5.8 J/cm3 and an efficiency of 77%. Further electric properties measurements and structure characterizations indicate that the moderate enhancement of permittivity can be ascribed to the doping of TiO2 nanoparticles, and the improved breakdown strength is caused by blending of PMMA with good insulating properties. Our results might provide a promising approach to develop high-performance energy-storage dielectric materials concerning the synergistic effect of blending and nanocomposite.

Organic ferroelectric field‐effect transistor memories with poly(vinylidene fluoride) gate insulators and conjugated semiconductor channels: a review

AbstractOrganic electronics have attracted considerable interest because of their low temperature solution processability, versatile material synthesis and compatibility with a wide range of traditional fabrication methods such as rod‐coating, inkjet and roll‐to‐roll printing techniques. Organic ferroelectric field‐effect transistors (OFeFETs) with a three‐terminal device architecture have ferroelectric thin films as gate insulator layers and semiconductor films as charge transport channel layers. OFeFETs have been demonstrated with non‐volatile memory functions that can retain their high or low conductive states in the semiconductor channel when the power is turned off. The reversible polarization switching in the ferroelectric gate insulator layer between two stable polarized states provides the basis for binary coded memory functions. In this review, we summarize recent development of OFeFETs based on ferroelectric poly(vinylidene fluoride) dielectrics and organic semiconductor channels. © 2020 Society of Chemical Industry

Electrical properties of yttrium-doped hafnium-zirconium dioxide thin films prepared by solution process for ferroelectric gate insulator TFT application

Ferroelectric yttrium-doped hafnium-zirconium dioxide (Y-HZO) thin films were fabricated by solution process on Pt/Ti/SiO2/Si substrates. Both metal–ferroelectric–metal (MFM) structures with Pt top electrode and metal–ferroelectric–semiconductor (MFS) structures with indium tin oxide (ITO) top electrode were fabricated and characterized. Solution-derived Y-HZO films annealed at 600 °C–800 °C showed ferroelectric properties which were confirmed by polarization–voltage loops (P–V) and capacitance–voltage (C–V) curves. The ferroelectric properties of Y-HZO were superior to those of undoped HZO, Y-doped HfO2 and undoped HfO2 samples. C–V curves showed clear butterfly loops with depletion of top ITO layer in the case of MFS, while no depletion was observed in the case of MFM structures. Large memory window was obtained for MFS structures and ferroelectric properties were observed even after high temperature annealing process during the solution deposition of ITO electrodes. These results suggest that a solution processed Y-HZO is a promising candidate for ferroelectric gate thin film transistor.

Enhanced Thermal Hall Effect in Nearly Ferroelectric Insulators.

In the context of recent experimental observations of an unexpectedly large thermal Hall conductivity, κ_{H}, in insulating La_{2}CuO_{4} (LCO) and SrTiO_{3} (STO), we theoretically explore conditions under which acoustic phonons can give rise to such a large κ_{H}. Both the intrinsic and extrinsic contributions to κ_{H} are large in proportion to the dielectric constant, ε, and the "flexoelectric" coupling, F. While the intrinsic contribution is still orders of magnitude smaller than the observed effect, an extrinsic contribution proportional to the phonon mean-free path appears likely to account for the observations, at least in STO. We predict a larger intrinsic κ_{H} in certain insulating perovskites.

Achieving Remarkable Amplification of Energy-Storage Density in Two-Step Sintered NaNbO3-SrTiO3 Antiferroelectric Capacitors through Dual Adjustment of Local Heterogeneity and Grain Scale.

Antiferroelectric (AFE) materials exhibit outstanding advantages against linear or ferroelectric (FE) dielectrics in high-performance energy-storage capacitors. However, their energy-storage performances are usually restricted by both extremely large hysteresis and insufficiently high driving field of the AFE-FE phase transition, which has been a longstanding issue to be overcome in the community. In this work, we report a two-step sintered 0.83NaNbO3-0.17SrTiO3 (NN-ST) lead-free relaxor AFE R-phase ceramic with high relative density of ≥95% and large spans of average grain sizes from 1.2 to 8.2 μm, strikingly achieving a giant amplification of recoverable energy-storage density (Wrec) by 176%. Analyses of permittivity-temperature curves, Raman spectrum and microstructure demonstrate that remarkably enhanced Wrec values should be ascribed to the dual adjustment of local heterogeneity (nanoscale) and grain scale (microscale), resulting in the enhanced threshold field strength for dielectric breakdown and the increased critical electric fields for the AFE-FE phase transition. A high Wrec ≈ 1.60 J/cm3, a fast discharging rate t0.9 ≈ 520 ns, large current density ∼788 A/cm2, and large power density ∼55 MW/cm3 are achieved at room temperature in the NN-ST ceramic sample with an average grain size of ∼1.2 μm. These results suggest that the multiscale structure regulation should be an efficient way for achieving enhanced energy-storage properties in NN-ST relaxor AFE ceramics through a two-step sintering technique.

Two-dimensional ligand-functionalized plumbene: A promising candidate for ferroelectric and topological order with a large bulk band gap

Abstract Multifunctional two-dimensional (2D) materials has been attracted attentions to explore due to their versatile applications in electronic devices. Ferroelectric and topological materials have separately attracted investigated recently. However, materials with two properties coexisting are little known. 2D materials with coexisting topological and ferroelectric ordering have been the focus of 2D condensed matter physics in recent years, and their interaction in a single system may make important untapped phenomena and applications possible. Here, based on first-principles calculations, we demonstrate a class of ferroelectric topological insulators (FETIs) in CH2OCH3-functionalized plumbene (Pb–CH2OCH3). We find that the large nontrivial band gap of Pb–CH2OCH3 reaching 0.80 eV, which is introduced by the orbital filtering effect in the presence of spin-orbit coupling (SOC). Noticeably, the in-plane spontaneous polarization can be engineered by rotating the CH2OCH3 molecule at the surface of Plumbene. These results on the combination of topological and ferroelectric properties may provide a new platform for the development of microelectronic devices and the application of spintronics at room temperature.

Wave propagation on a ferroelectric liquid crystal based acoustic metamaterial

In the present work, the acoustic band structure of a 2D phononic crystal (PnC) containing an organic ferroelectric (low molecular weight liquid crystal polimer in C-smectic phase - LMWLCS) and topological insulator (GeTe) were investigated by the finite element method and experimentally. 2D PnC with square lattices composed of GeTe cylindrical rods embedded in the LMWLCS matrix are studied to find the allowed and stop bands for the waves of certain energy. Phononic band diagram ω = ω(k) for a 2D PnC along the Г-X-M-Г path in the square Brillouin zone shows few stop bands in the frequency range between 10–110 kHz.

Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.

A simulation study on low voltage operability of hafnium oxide based ferroelectric FET memories

Lower limit of operable voltage for ferroelectric field effect transistor memories using hafnium oxide based ferroelectric gate dielectrics was estimated using circuit simulations. Assuming realistic array architecture, memory weakening by disturbs and restrictions set by sneak current were taken into account. For modeling ferroelectricity, a continuous Preisach model of hysteresis was used. The results show that the lowest possible operation voltage, not including variability and reliability margin, will be around ±2 V. It was found that moderate reduction of remanent polarization is beneficial for lowering both operation voltage and interfacial layer electric field stress.

Switching On/Off Negative Capacitance in Ultrathin Ferroelectric/Dielectric Capacitors.

Ferroelectric (FE) and dielectric (DE) insulator bilayer stacks provide a promising gate for low-power microelectronic devices. To fully realize the FE polarization switching, the DE layer must be ultrathin in the FE/DE bilayer stack. Motivated by this, this work presents the first successful fabrication and characterization of Fe/FeOx/Al2O3/Fe FE/DE bilayer capacitors using in vacuo atomic layer deposition (ALD) with a total FE/DE stack thickness <3-4 nm. A key tuning parameter in generating the FE/DE bilayer capacitors is the thickness of an Al wetting layer between the bottom Fe electrode and the ALD-Al2O3 DE layer. At a large thickness in exceeding 1.0 nm, high-quality conventional DE capacitors of 2.2 nm thick ALD-Al2O3 were obtained with dielectric constant (εr) ∼8.0 that is close to εr ∼ 9.2 for the Al2O3 bulk single crystal with an effective oxide thickness of 1.0 nm. By reducing the Al wetting layer thickness to below 1.0 nm, a thin ferroelectric FeOx interfacial layer of a thickness of 1-2 nm forms, enabling the achievement of a FeOx/Al2O3 FE/DE bilayer capacitor with static negative capacitance. Since all ferroelectric materials are piezoelectric, we show that a dynamic switching on/off of the negative capacitance can be achieved under the application of an external force on the ultrathin FE/DE capacitors through manipulation of the electric dipoles. This result not only provides a viable approach for generating ultrathin FE/DE bilayer capacitors but also offers a promising solution to low-power consumption microelectronics.