Ferroelectric Hafnium Zirconium Oxide Research Articles

A Non-Reciprocal Filter Using Asymmetrically Transduced Micro-Acoustic Resonators

This letter reports a non-reciprocal filter based on the use of nonlinearities in high quality-factor ( $ {Q}$ ) silicon micro-acoustic resonators with asymmetric piezoelectric transducers. The two-port resonators are created by the integration of 120-nm piezoelectric aluminum nitride and 10-nm ferroelectric hafnium–zirconium-oxide transducers atop of 70-nm single-crystal silicon. The asymmetric electromechanical transduction architecture results in highly contrasted power-handing of the micro-acoustic resonator when excited at different ports, resulting in non-reciprocal transmission response for excitation powers beyond a certain threshold. A proof-of-concept filter at 253 MHz with 0.25% −3-dB bandwidth is implemented through electrical coupling of two asymmetrically transduced resonators with individual ${Q}$ of ~870. The filter demonstrates a non-reciprocal transmission ratio of ~16 dB for input power exceeding 5 dBm.

Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs

Negative capacitance (NC) field-effect transistors (FETs) with 2-D semiconducting channels have become increasingly attractive due to their ability to produce sub-60 mV/dec switching behavior in a physically scalable device. However, it has yet to be determined how gate control, including threshold voltage, of 2-D NC-FETs is impacted by gate dielectric composition, along with dielectric and ferroelectric layer thicknesses. Here, we show the threshold voltage shifts positively under increasing ferroelectric thickness and negatively with increasing dielectric thickness. This shifting behavior is observed in devices without an interfacial metal layer between the ferroelectric hafnium zirconium oxide (HfZrO2 or HZO) and dielectric. Because the interface between the ferroelectric and dielectric is critical in driving NC behavior, we also study 2-D NC-FETs with 4 nm HZO paired with different dielectrics. These results reveal that the HZO/Al2O3 interface is more favorable than either the HZO/ZrO2 or HZO/HfO2 interfaces. Finally, the impact of an interfacial metal layer is discussed by comparing the 2-D NC-FET performance of similar devices with and without this layer.

Direct Correlation of Ferroelectric Properties and Memory Characteristics in Ferroelectric Tunnel Junctions

Ferroelectric memories have made big advancements in the last years due to the discovery of ferroelectricity in already widely used hafnium oxide. Here we investigate ferroelectric tunnel junctions (FTJ) consisting of a ferroelectric hafnium zirconium oxide layer and a dielectric aluminum oxide layer. By varying the set and reset amplitude and pulse width the fraction of reversed ferroelectric domains can be controlled. Due to the statistical distribution of the coercive voltage the current can be tuned between the minimum off-state and maximum on-state current. This leads to possible multi-level information storage in our FTJs. In this paper a detailed study of the set/reset operation and the intermediate current levels is presented. Furthermore, the endurance properties of the memory device can be directly correlated to the wake-up and fatigue phenomena in the ferroelectric layer. While the usability of the memory window is still limited by the initial polarization increase and ultimately by the hard breakdown of the device, a further optimization of the ferroelectric layer itself and the ferroelectric/dielectric interface can directly improve the viability of the tunnel junction. Finally, we show that the current of our FTJs scales as expected and reproducible results across different devices are obtained.

Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor.

P-type two-dimensional steep-slope negative capacitance field-effect transistors are demonstrated for the first time with WSe2 as channel material and ferroelectric hafnium zirconium oxide in gate dielectric stack. F4-TCNQ is used as p-type dopant to suppress electron leakage current and to reduce Schottky barrier width for holes. WSe2 negative capacitance field-effect transistors with and without internal metal gate structures and the internal field-effect transistors are compared and studied. Significant SS reduction is observed in WSe2 negative capacitance field-effect transistors by inserting the ferroelectric hafnium zirconium oxide layer, suggesting the existence of internal amplification (∼10) due to the negative capacitance effect. Subthreshold slope less than 60 mV/dec (as low as 14.4 mV/dec) at room temperature is obtained for both forward and reverse gate voltage sweeps. Negative differential resistance is observed at room temperature on WSe2 negative capacitance field-effect-transistors as the result of negative capacitance induced negative drain-induced-barrier-lowering effect.

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

Steep-slope hysteresis-free negative capacitance MoS2 transistors.

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

β-Ga2O3 Nanomembrane Negative Capacitance Field-Effect Transistors with Steep Subthreshold Slope for Wide Band Gap Logic Applications.

Steep-slope β-Ga2O3 nanomembrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in the gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate-voltage sweeps with a minimum value of 34.3 mV/dec at the reverse gate-voltage sweep and 53.1 mV/dec at the forward gate-voltage sweep at VDS = 0.5 V. Enhancement-mode operation with a threshold voltage of ∼0.4 V is achieved by tuning the thickness of the β-Ga2O3 membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis, and enhancement-mode β-Ga2O3 NC-FETs are promising as an nFET candidate for future wide band gap complementary metal-oxide-semiconductor logic applications.

Doped Hf0.5Zr0.5O2 for high efficiency integrated supercapacitors

Applications for integrated energy storage and pulse-power devices may have found opportunities in the emergence of the ferroelectric hafnium-zirconium oxide thin film system. To explore the boundaries of this material thin film system, 10 nm thick binary Hf0.5Zr0.5O2 (HZO) thin films are doped with Al or Si (Al or Si-doped HZO). The added dopants provide a distinct shift in behavior from ferroelectric to antiferroelectric characteristics. Si-doped Hf0.5Zr0.5O2 thin films exhibited a larger than 50 J/cm3 energy storage density with an efficiency of over 80%. The Si-doped Hf0.5Zr0.5O2 thin films were cycled 109 times up to 125 °C and maintained a robust 35 J/cm3 energy storage density and greater than 80% efficiency. Al-doped Hf0.5Zr0.5O2 thin films exhibited a larger switching field, leading to a smaller energy storage density and less robust cycling properties than Si-doped Hf0.5Zr0.5O2.