Ferroelectric Gate Research Articles

Design space exploration of hysteretic negative capacitance ferroelectric FETs based on static solutions of Landau–Khalatnikov model for nonvolatile memory applications

Systematic design space exploration of negative capacitance ferroelectric field-effect transistors (FeFETs) for nonvolatile memory operations was performed, combining load line analyses and circuit simulations. Unlike those FeFETs aiming at a steep subthreshold slope, the key design target here is to achieve bi-stable current versus voltage FET characteristics with appropriate hysteresis width (i.e. memory window). Remanent polarization, coercive voltage, and interfacial layer thickness were selected as design parameters. The results show that, if a ferroelectric gate dielectric film obeying ideal single-domain Landau–Khalatnikov model dynamics with reduced remanent polarization is available, ultralow voltage nonvolatile memories operating with sub-one volt voltage swing would become possible. An interesting feature of the negative capacitance FeFETs is that, unlike conventional multiple domain FeFETs, the memory window can be adjusted to a much smaller value than twice the coercive voltage. The lowered remanent polarization is required to suppress the depolarization field to an acceptable level for reliability. It is proposed that considering the abrupt polarization switching, three-transistor and two-transistor memory cells would be suitable for working and code storage memories, respectively.

Indium oxide and indium-tin-oxide channel ferroelectric gate thin film transistors with yttrium doped hafnium-zirconium dioxide gate insulator prepared by chemical solution process

Ferroelectric gate transistor (FGT) with yttrium doped hafnium-zirconium dioxide (Y-HZO) gate insulator and oxide channel with various thicknesses of In2O3 and ITO were fabricated by chemical solution deposition. First, ferroelectric properties of Y-HZO in the metal-ferroelectric-semiconductor structure with 5–22 nm thick In2O3 and 6–24 nm thick ITO, have been confirmed by polarization–voltage and capacitance–voltage (C–V) characteristics. The C–V curves showed clear butterfly loops showing the depletion of In2O3 and ITO layer. Secondly, the device performance of FGTs has been evaluated with various thicknesses of In2O3 and ITO channel layer. The fabricated FGTs exhibited typical n-channel transistor operation with a counterclockwise hysteresis loop due to the ferroelectric nature of the Y-HZO-gate insulator. It was found that FGT shows a low subthreshold voltage swing, high on/off drain current ratio of 106, large on current, and memory window.

Ferroelectric Gating of Narrow Band-Gap Nanocrystal Arrays with Enhanced Light–Matter Coupling

As narrow band gap nanocrystals become a considerable building block for the design of infrared sensors, device design needs to match their actual operating conditions. While in the near and shortwave infrared, room-temperature operation has been demonstrated, longer wavelengths still require low-temperature operations and thus specific design. Here, we discuss how field-effect transistors (FETs) can be compatible with low-temperature detection. To reach this goal, two key developments are proposed. First, we report the gating of nanocrystal films from SrTiO3 which leads to high gate capacitance with leakage and breakdown free operation in the 4–100 K range. Second, we demonstrate that this FET is compatible with a plasmonic resonator whose role is to achieve strong light absorption from a thin film used as the channel of the FET. Combining three resonances, broadband absorption from 1.5 to 3 μm reaching 30% is demonstrated. Finally, combining gate and enhanced light–matter coupling, we show that detectivity can be as high as 1012 Jones for a device presenting a 3 μm cutoff wavelength and 30 K operation.

Performance Enhancement and Signal Distortion Analysis of Virtually Doped Nanotube Tunnel FET with Embedded Ferroelectric Gate Oxide

This paper demonstrates the effect of ferroelectric gate oxide on the electrostatic doped nanotube tunnel field-effect transistor (FE-ED-NTTFET). The proposed device is a dopingless device, and the electrostatic doped method is used for the operation of the device. For electrostatic doped operation, the operating source voltage (VS) for the proposed device is −1.2 V. The intrinsic doping is used throughout the device. The thin ferroelectric material with a width of 2 nm is used as the gate oxide, to improve the performance of the proposed FE-ED-NTTFET device. For the detailed investigation of the proposed FE-ED-NTTFET device, the following parameters are taken into consideration such as device parameters, analogue parameters, and linearity parameters. In device parameters, energy band diagram, quasi Fermi-level of electron and hole, electron/hole mobility, electric filed, non-local tunneling (BTBT), and hole/electron concentration are taken into consideration. In analogue parameters ON current, OFF current, ION/IOFF current ratio, threshold voltage, and sub-threshold swings are considered. For small-signal analysis linearity parameters such as TGF, cut-off frequencies, HD2, HD3, VIP2, VIP3, IIP3, and IMD3 have been discussed. The proposed FE-ED-NTTFET device shows the higher ON current (ION) 6.24uA, lower OFF current (IOFF) order of 10−17 A, higher ION/IOFF current ratio 1*1012, and better sub-threshold swing (SS) 12 mV/decade for gate voltage (VGS) 1.2 V.

A method for estimating defects in ferroelectric thin film MOSCAPs

We propose a capacitance measurement scheme that enables quantitative characterization of ferroelectric thin films integrated on semiconductors. The film defect density is estimated by measurements of the CV hysteresis and frequency dispersion, whereas important device parameters such as memory window and endurance can be extracted by a unidirectional CV method. The simple measurement scheme and the usage of metal-oxide-semiconductor capacitors rather than MOSFETs make the proposed methods suitable for the future optimization of ferroelectric field effect transistor and negative capacitance field effect transistor gate stacks. Specifically, we present data for the narrow bandgap semiconductor InAs and show that low temperature characterization is critical to reduce the influence of the minority carrier response; however, the methods should be transferrable to room temperature for semiconductors with a wider bandgap. Our results clearly indicate that the defect density of the HfxZr1−xO2 (HZO) films increases at the crystallization temperature, but the increase is modest and remains independent of the annealing temperature at even more elevated temperatures. It is also shown that the shrinkage of the memory window caused by field cycling is not accompanied by an increase in defect density.

Impact of oxide gate electrode for ferroelectric field-effect transistors with metal-ferroelectric-metal-insulator-semiconductor gate stack using undoped HfO2 thin films prepared by atomic layer deposition

Ferroelectric field-effect transistors (FETs) with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gate stack were fabricated and characterized to elucidate the key process parameters and to optimize the process conditions for guaranteeing nonvolatile memory operations of the device when the undoped HfO2 was employed as ferroelectric gate insulator. The impacts of top gate (TG) for the MFM part on the memory operations of the MFMIS-FETs were intensively investigated when the TG was chosen as metal Pt or oxide ITO electrode. The ferroelectric memory window of the MFMIS-FETs with ITO/HfO2/TiN/SiO2/Si gate stack increased to 3.8 V by properly modulating the areal ratio between two MFM and MIS capacitors. The memory margin as high as 104 was obtained during on- and off-program operations with a program pulse duration as short as 1 μs. There was not any marked degradation in the obtained memory margin even after a lapse of retention time of 104 s at 85 °C and repeated program cycles of 10,000. These obtained improvements in memory operations resulted from the fact that the choice of ITO TG could provide effective capping effects and passivate the interfaces.

Effect of Curie Temperature on Ferroelectric Tunnel FET and Its RF/Analog Performance.

In this article, a numerical simulation study for the ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET) has been presented. The performance of the device is analyzed following Landau's theory and its behavior in the temperature range of 200-300 K. A minimum subthreshold swing and maximum transconductance is obtained around the Curie temperature ( TC ) of 580 ± 10 K for the simulated device. The simulation result is supported by the simple analytical model. The temperature sensitivity analysis is studied on different analog and RF figure of merits for Ferro-TFET. In this study, the Ferro-TFET shows the remarkable result in reducing the detrimental effect of mobility degradation at high gate voltage and performance degradation at high temperatures as compared to conventional TFETs and MOSFET. Therefore, at Curie temperature, the operation of the Ferro-TFET shows the remarkable results for analog and RF applications.

(Invited) Hafnia Ferroelectric Device for Semiconductor, Sensor, and Display Applications

For the ferroelectric material with the conventional perovskite crystal structure and the chemical formula of ABO3, the charge neutral level is located close to the conduction band edge, and when forming a device, it causes a high leakage current due to low Schottky barrier height. Therefore, a relatively thick ferroelectric thin film was required, which was not suitable for the existing CMOS technology that is evolving through miniaturization. Meanwhile, ferroelectric properties were discovered in hafnia in 2011, and the ferroelectric properties of hafnia is observed in an orthorhombic crystal structure. Due to its simple structure and excellent CMOS process compatibility, it has received much attention for ferroelectric hafnia thin films and various application technologies using them. In this report, we will look at various application technologies using hafnia ferroelectrics, and we will examine the characteristics of hafnia ferroelectrics suitable for each device.Ferroelectrics are one of the most crucial inorganic materials due to their fantastic functionalities and their remarkable properties in response to electrical and mechanical stimuli [1-4]. As a representative ferroelectric material, the perovskite-type ferroelectrics materials have received intense attention. However, the electrical properties of perovskite materials become deteriorating with the scaling of area and thickness, which doesn't allow to make use it for a scaled device [1-2]. In particular, the process incompatibility between Si technology and the perovskite material has not been overcome and their applications are limited. Thus, the exploration for ferroelectric materials having outstanding process compatibility with Si technology has been highly required [3-4].In 2011, hafnia-based ferroelectric material was reported and the most surprising feature of this material is its simple chemical composition and thermodynamic stability [5-6], which has outstanding process compatibility with Si-based semiconductor technology [1]. Hafnia-based materials are actually being utilized as alternative gate dielectric layers in MOSFET because of their high-k value. The ferroelectric field effect transistor (FeFET) is being considered as the DRAM cell in next generation [7-8]. Multi-level FeFETs are reported not only for NAND flash but also for processing-in-memory architecture [9]. In addition, recent intensive studies have revealed new ferroelectric applications including sensor, logic and energy devices. In this presentation, we will review various device applications of hafnia ferroelectric thin films.In our research, we have developed hafnia-based ferroelectric materials, processes and devices. The different characteristics of the hafnia ferroelectric materials are required for NAND Flash, processing-in-memory, DRAM, sensor, and thin-film transistors for display. We are making it the best fit for each application by the hafnia ferroelectric process development, gate stack and device design. In this presentation, we will examine the issues and requirements of each of these devices, see how we are solving these issues, summarize the remaining issues to date, and discuss the possibility to further improve speed, reliability and the memory window.

Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating.

In this work, we demonstrate high-performance indium-tin-oxide (ITO) transistors with a channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. An on-current of 0.243 A/mm is achieved on submicron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ω·mm and a low contact resistivity of 1.1 × 10-7 Ω·cm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin-film transistors, including large-area wafer-size nanometer thin-film formation, low contact resistance and contact resistivity, an atomic thin channel being immune to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line complementary metal-oxide-semiconductor application.

Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET

We have investigated the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET). Extensive simulations show that using a hetero-dielectric gate architecture in the lateral direction (non-ferroelectric/ferroelectric/non-ferroelectric) results in more desirable analog/RF characteristics. The proposed structure is compared with conventional tunnel field effect transistors (TFETs) and ferroelectric TFET (FeTFET). Simulation results manifest that HD-FeTFET is superior to other compared structures, and benefits from both ferroelectric and hetero-dielectric structure. Negative capacitance effect in ferroelectric causes a step-up voltage transformer, as a result the subthreshold swing decreases. Owing to two different dielectric constants in the hetero-dielectric structure, the electric field enhances; thereby, the on-state current increases. In this paper, important analog/RF figures of merit, such as cut-off frequency (fT), maximum oscillation frequency (fmax), transconductance frequency product, and intrinsic time delay (τ), are investigated. Also, linearity parameters including VIP2, VIP3, IIP3, and the 1-dB compression point are considered. We achieve average sub-threshold swing of 14 mV for 5 decades for HD-FeTFET, and is improved by ∼ 48% and ∼ 30% for TFET and FeTFET, respectively. Moreover, the ION/IOFF ratio and the on-state current for the proposed structure are 1011 and 5.3 × 10−7 (A/μm), respectively.

Demonstration of Wide Bandgap AlGaN/GaN Negative‐Capacitance High‐Electron‐Mobility Transistors (NC‐HEMTs) Using Barium Titanate Ferroelectric Gates

AbstractA negative‐capacitance high electron mobility transistor (NC‐HEMT) with low hysteresis in the subthreshold region is demonstrated in the wide bandgap AlGaN/GaN material system using sputtered BaTiO3 as a “weak” ferroelectric gate in conjunction with a conventional SiNx dielectric. An enhancement in the capacitance for BaTiO3/SiNx gate stacks is observed in comparison to control structures with SiNx gate dielectrics directly indicating the negative capacitance contribution of the ferroelectric BaTiO3 layer. A significant reduction in the minimum subthreshold slope for the NC‐HEMTs is obtained in contrast to standard metal‐insulator‐semiconductor HEMTs with SiNx gate dielectrics—97.1 mV dec−1 versus 145.6 mV dec−1—with almost no hysteresis in the ID–VG transfer curves. These results are promising for the integration of ferroelectric perovskite oxides with III‐Nitride devices toward NC‐field‐effect transistor switches with reduced power consumption.

Interfacial charge and strain effects on lanthanum doped barium stannate thin film under ferroelectric gating

Interfacial charge and strain are two coupling effects in semiconductor/ferroelectric epitaxial heterostructures, which are pivotal for use in tailoring functionalities in devices. In this work, La0.04Ba0.96SnO3/0.7Pb(Mg1/3Nb2/3)O3–0.3PbTiO3 heterostructures with varying film thicknesses were prepared in order to understand both charge and strain's contributions to the electric-field induced resistance change. The relative resistance change to the lattice strain remains almost unchanged in those thicker films, while increases a little bit in those thinner films. This slight increase is related to the substrate constraint near the interface and follows Freund's strain relaxation model during the dynamic strain induced by the piezoelectric switch. A depletion layer model was also established to simulate the electroresistance variation from the interfacial charge effect. The depletion layer involves an equilibrium between capture and release of electrons by the acceptor-like defects near the interface region. The resistance change vs electric field evolves from a butterfly-like shape to a square-like when decreasing the film thickness, due to the joint effect of strain and interfacial polarization screening charge. This study provides an insight into understanding heteroepitaxial coupling and exploring their potential applications in oxide electronic devices.

Design and fabrication of field-plated normally off β -Ga2O3 MOSFET with laminated-ferroelectric charge storage gate for high power application

In this work, an enhancement-mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) has been achieved by incorporating a laminated-ferroelectric charge storage gate (L-FeG) structure [Al2O3/HfO2/Al2O3/Hf0.5Zr0.5O2 (HZO) of 10/5/2/16 nm]. The band diagram between L-FeG dielectrics (Al2O3, HfO2, and HZO) and β-Ga2O3 was determined by x-ray photoelectron spectroscopy. After applying a gate pulse with an intensity of +18 V and width of 1 ms, the saturation current of the E-mode device was measured to be 23.2 mA/mm, which shows a negligible current reduction compared to that of 22.1 mA/mm in a depletion- (D-) mode device. In addition, the threshold voltage (VTH) is only shifted by 2.76% and 2.18%, respectively, after applying the gate stress and gate-drain stress of 15 V for 104 s. Meanwhile, a high breakdown voltage of 2142 V and specific on-resistance (RON,sp) of 23.84 mΩ·cm2 were also achieved, which correspond to a state-of-art high power figure of merit of 192.5 MW/cm2, showing the great potential of combing the ferroelectric gate stack and lateral Ga2O3 MOSFET as next generation power devices.

Evaluation of polarization characteristics in metal/ferroelectric/semiconductor capacitors and ferroelectric field-effect transistors

In this study, we propose a measurement technique for evaluating ferroelectric polarization characteristics in ferroelectric field-effect transistors (FeFETs). Different from standard metal/ferroelectric/metal capacitors, the depletion and inversion phenomena in semiconductor substrates have to be carefully taken into account when evaluating the ferroelectric properties using fast voltage sweep as input. The non-equilibrium deep depletion is found to be the limiting factor for the accurate evaluation of ferroelectric properties in metal/ferroelectric/semiconductor capacitors. By connecting the source, the drain, and the substrate of the FeFET together during the polarization measurement, the deep depletion can be suppressed and the ferroelectricity of the ferroelectric gate can be accurately evaluated. The present technique is a powerful method for capturing the polarization states in FeFETs, enabling new approaches for device characterization and fundamental study, and overcomes the limitation found in the conventional polarization measurement on two-terminal metal/ferroelectric/semiconductor capacitors.

Investigation of Electrical Characteristics in a Ferroelectric L-Patterned Gate Dual Tunnel Diode TFET.

This paper presents a ferroelectric L-patter- ned gate TFET with heavily doped (p++ type) dual tunnel diodes (DTDs), which analyzes the concept of negative capacitance as well as vertical tunneling. The tunnel junction and the channel direction are perpendicular that facilitates a broad area of the tunnel junction. Furthermore, ON current is enhanced due to the introduction of n+ pocket. To exaggerate the [Formula: see text] ratio, the device architecture is designed systematically by optimizing the ferroelectric and pocket thickness. The cumulated holes are extricated by the tunnel current produced by the DTDs, reducing the kink effect. An enhanced ON current of the order of 10-5 A/ [Formula: see text] with a minimal subthreshold swing (SS) of 29 mV/decade is achieved. The characteristics of the proposed TFET structure is compared with the existing TFET designs, and the proposed design proves to be an appropriate device for high performance and ultra-low-power applications.

A flexible artificial intrinsic-synaptic tactile sensory organ

Imbuing bio-inspired sensory devices with intelligent functions of human sensory organs has been limited by challenges in emulating the preprocessing abilities of sensory organs such as reception, filtering, adaptation, and sensory memory at the device level itself. Merkel cells, which is a part of tactile sensory organs, form synapse-like connections with afferent neuron terminals referred to as Merkel cell-neurite complexes. Here, inspired by structure and intelligent functions of Merkel cell-neurite complexes, we report a flexible, artificial, intrinsic-synaptic tactile sensory organ that mimics synapse-like connections using an organic synaptic transistor with ferroelectric nanocomposite gate dielectric of barium titanate nanoparticles and poly(vinylidene fluoride-trifluoroethylene). Modulation of the post-synaptic current of the device induced by ferroelectric dipole switching due to triboelectric-capacitive coupling under finger touch allowed reception and slow adaptation. Modulation of synaptic weight by varying the nanocomposite composition of gate dielectric layer enabled tuning of filtering and sensory memory functions.

In‐Depth Atomic Mapping of Polarization Switching in a Ferroelectric Field‐Effect Transistor

AbstractThe ferroelectric control of a Mott transistor is a promising strategy for nonvolatile low‐power electronics. Understanding the fundamental limits of the ferroelectric‐field effect is challenging, as the relevant length scales are restricted to a few atomic planes within the interface. Here, the polarization switching process of a prototypical ferroelectric Mott transistor combining BiFeO3, a ferroelectric material with a large polarization, and (Ca,Ce)MnO3, a charge‐transfer insulator in which a few percent of Ce doping triggers a metal–insulator transition is investigated. While scanning probe microscopy indicates a complete switching of the ferroelectric gate, in‐depth atomic‐scale polarization mapping with scanning transmission electron microscopy reveals incomplete polarization reversal at the interface. Therefore, transport measurements show that the electronic properties of the Mott channel are virtually unchanged by the polarization direction. Nevertheless, in nanometer size areas where interfacial polarization switching occurs, dramatic changes of the electronic properties of (Ca,Ce)MnO3 are revealed. These results indicate how the performance of mesoscale Mott devices is hindered, and at the same time reveal the possibility of nanoscale energy‐efficient Mott transistors.

A van der Waals Synaptic Transistor Based on Ferroelectric Hf0.5Zr0.5O2 and 2D Tungsten Disulfide

AbstractNeuromorphic computing on the hardware level is promising for performing ever‐increasing data‐centric tasks owing to its superiority to conventional von Neumann architecture in terms of energy efficiency and learning ability. One key aspect to its implementation is the development of artificial synapses that can effectively emulate the multiple functionalities exhibited by their biological counterparts. Here, building on an inorganic ferroelectric gate stack integrated with a 2D layered semiconductor (WS2), a new type of ferroelectricity‐based synaptic transistor that differs from those relying on interface traps or floating gate configuration is reported. By virtue of a 6 nm thick ferroelectric hafnium zirconium oxide by atomic layer deposition and postannealing treatment, the device shows a channel resistance change ratio above 105 corresponding to opposite ferroelectric polarization direction. Furthermore, by applying electrical stimulus to the gate, it demonstrates good capability to mimic various synaptic behaviors including long‐term potentiation, long‐term depression, spike‐amplitude‐dependent plasticity, and spike‐rate‐dependent plasticity. Given the inherent compatibility of the ferroelectric gate stack with existing fabrication technology, and the reliability of ferroelectricity engineering, this work paves the way toward practical implementation of synaptic devices in neuromorphic circuits.

Organic ferroelectric field‐effect transistor memories with poly(vinylidene fluoride) gate insulators and conjugated semiconductor channels: a review

AbstractOrganic electronics have attracted considerable interest because of their low temperature solution processability, versatile material synthesis and compatibility with a wide range of traditional fabrication methods such as rod‐coating, inkjet and roll‐to‐roll printing techniques. Organic ferroelectric field‐effect transistors (OFeFETs) with a three‐terminal device architecture have ferroelectric thin films as gate insulator layers and semiconductor films as charge transport channel layers. OFeFETs have been demonstrated with non‐volatile memory functions that can retain their high or low conductive states in the semiconductor channel when the power is turned off. The reversible polarization switching in the ferroelectric gate insulator layer between two stable polarized states provides the basis for binary coded memory functions. In this review, we summarize recent development of OFeFETs based on ferroelectric poly(vinylidene fluoride) dielectrics and organic semiconductor channels. © 2020 Society of Chemical Industry

Electrical properties of yttrium-doped hafnium-zirconium dioxide thin films prepared by solution process for ferroelectric gate insulator TFT application

Ferroelectric yttrium-doped hafnium-zirconium dioxide (Y-HZO) thin films were fabricated by solution process on Pt/Ti/SiO2/Si substrates. Both metal–ferroelectric–metal (MFM) structures with Pt top electrode and metal–ferroelectric–semiconductor (MFS) structures with indium tin oxide (ITO) top electrode were fabricated and characterized. Solution-derived Y-HZO films annealed at 600 °C–800 °C showed ferroelectric properties which were confirmed by polarization–voltage loops (P–V) and capacitance–voltage (C–V) curves. The ferroelectric properties of Y-HZO were superior to those of undoped HZO, Y-doped HfO2 and undoped HfO2 samples. C–V curves showed clear butterfly loops with depletion of top ITO layer in the case of MFS, while no depletion was observed in the case of MFM structures. Large memory window was obtained for MFS structures and ferroelectric properties were observed even after high temperature annealing process during the solution deposition of ITO electrodes. These results suggest that a solution processed Y-HZO is a promising candidate for ferroelectric gate thin film transistor.