Ferroelectric Gate Research Articles

Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability

This paper investigates In[Formula: see text]Ga[Formula: see text]As/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO2 as dielectric stack over SiO2 provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.

Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering

The superior size and power scaling potential of ferroelectric-gated Mott transistors makes them promising building blocks for developing energy-efficient memory and logic applications in the post-Moore’s Law era. The close to metallic carrier density in the Mott channel, however, imposes the bottleneck for achieving substantial field effect modulation via a solid-state gate. Previous studies have focused on optimizing the thickness, charge mobility, and carrier density of single-layer correlated channels, which have only led to moderate resistance switching at room temperature. Here, we report a record high nonvolatile resistance switching ratio of 38,440% at 300 K in a prototype Mott transistor consisting of a ferroelectric PbZr0.2Ti0.8O3 gate and an RNiO3 (R: rare earth)/La0.67Sr0.33MnO3 composite channel. The ultrathin La0.67Sr0.33MnO3 buffer layer not only tailors the carrier density profile in RNiO3 through interfacial charge transfer, as corroborated by first-principles calculations, but also provides an extended screening layer that reduces the depolarization effect in the ferroelectric gate. Our study points to an effective material strategy for the functional design of complex oxide heterointerfaces that harnesses the competing roles of charge in field effect screening and ferroelectric depolarization effects.

A Comparative Study of n- and p-Channel FeFETs with Ferroelectric HZO Gate Dielectric

This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs.

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.

Dual‐logic‐in‐memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

AbstractThe rapid advancement of AI‐enabled applications has resulted in an increasing need for energy‐efficient computing hardware. Logic‐in‐memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual‐logic‐in‐memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectric field‐effect transistors (vdW FeFETs). The proposed dual‐logic‐in‐memory device, which also acts as a two‐bit storage device, is a single bidirectional polarization‐integrated ferroelectric field‐effect transistor (BPI‐FeFET). It is fabricated by integrating an in‐plane vdW ferroelectric semiconductor SnS and an out‐of‐plane vdW ferroelectric gate dielectric material—CuInP2S6. Four reliable resistance states with excellent endurance and retention characteristics were achieved. The two‐bit storage mechanism in a BPI‐FeFET was analyzed from two perspectives: carrier density and carrier injection controls, which originated from the out‐of‐plane polarization of the gate dielectric and in‐plane polarization of the semiconductor, respectively. Unlike conventional multilevel FeFETs, the proposed BPI‐FeFET does not require additional pre‐examination or erasing steps to switch from/to an intermediate polarization, enabling direct switching between the four memory states. To utilize the fabricated BPI‐FeFET as a dual‐logic‐in‐memory device, two logical operations were selected (XOR and AND), and their parallel execution was demonstrated. Different types of logic operations could be implemented by selecting different initial states, demonstrating various types of functions required for numerous neural network operations. The flexibility and efficiency of the proposed dual‐logic‐in‐memory device appear promising in the realization of next‐generation low‐power computing systems.image

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials.

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60mVdec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state,and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Two-dimensional transition metal halide PdX 2 (X = F, Cl, Br, I): A promising candidate of bipolar magnetic semiconductors

Two-dimensional (2D) nanomaterials with bipolar magnetism show great promise in spintronic applications. Manipulating carriers’ spin-polarized orientation in bipolar magnetic semiconductor (BMS) requires a gate voltage, but that is volatile. Recently, a new method has been proposed to solve the problem of volatility by introducing a ferroelectric gate with proper band alignment. In this paper, we predict that the PdX 2 (X = F, Cl, Br, I) monolayers are 2D ferromagnetic BMS with dynamic stability, thermal stability, and mechanical stability by first-principles calculations. The critical temperatures are higher than the boiling point of liquid nitrogen and the BMS characteristics are robust against external strains and electric fields for PdCl2 and PdBr2. Then, we manipulate the spin-polarization of PdCl2 and PdBr2 by introducing a ferroelectric gate to enable magnetic half-metal/semiconductor switching and spin-up/down polarization switching control. Two kinds of spin devices (multiferroic memory and spin filter) have been proposed to realize the spin-polarized directions of electrons. These results demonstrate that PdCl2 and PdBr2 with BMS characters can be widely used as a general material structure for spintronic devices.

Investigation of time-dependent gate dielectric breakdown in recessed E-mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT)

The aim of achieving E-mode operations has led to the proposal of novel hybrid ferroelectric charge trap gate stack schemes. These schemes involve utilizing a combination of the charge trapping layer (CTL) and the ferroelectric laminated layer to positively shift the threshold voltage to a normally-off margin after initializing the gate pulse, thus achieving the Enhancement-mode (E-mode) characteristic. This study focuses on the forward gate bias time-dependent dielectric breakdown (TDDB) gate reliability in the E-Mode GaN MIS-HEMTs using ferroelectric charge trap gate stack (FEG-HEMT) with and without recess and investigates the impact of temperature on TDDB. The gate voltages required for operation with a 1 % failure rate over a 10-year period are 12.95 V and 10.22 V at 25 °C and 150 °C for both samples, respectively. Also, the examination of the stability of the recessed process by calculating the activation energies (0.7 eV) of both samples are demonstrated. The article also investigates the relationship between long-term reliability and short-term initialization by examining the transition point of the time-dependent failure curve.

Broadband Van-der-Waals Photodetector Driven by Ferroelectric Polarization.

The potential for various future industrial applications has made broadband photodetectors beyond visible light an area of great interest. Although most 2D van-der-Waals (vdW) semiconductors have a relatively large energy bandgap (>1.2eV), which limits their use in short-wave infrared detection, they have recently been considered as a replacement for ternary alloys in high-performance photodetectors due to their strong light-matter interaction. In this study, a ferroelectric gating ReS2 /WSe2 vdW heterojunction-channel photodetector is presented that successfully achieves broadband light detection (>1300nm, expandable up to 2700nm). The staggered type-II bandgap alignment creates an interlayer gap of 0.46eV between the valence band maximum (VBMAX ) of WSe2 and the conduction band minimum (CBMIN ) of ReS2 . Especially, the control of poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric dipole polarity for a specific wavelength allows a high photoresponsivity of up to 6.9 × 103 A W-1 and a low dark current below 0.26 nA under the laser illumination with a wavelength of 405nm in P-up mode. The achieved high photoresponsivity, low dark current, and full-range near infrared (NIR) detection capability open the door for next-generation photodetectors beyond traditional ternary alloy photodetectors.

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Exploring the Physical Origin of the Negative Capacitance Effect in a Metal–Ferroelectric–Metal–Dielectric Structure

AbstractThe ferroelectric negative capacitance (NC) draws a great deal of attention for low‐power negative capacitance field‐effect transistors (NCFET) and NC capacitors. The fabrication of steep‐slope FET (subthreshold swing < 60mVdec−1) is reported, followed by modeling approaches. While the device fabrication favors a ferroelectric gate structure without interlayer metal, many NCFET models adopt interlayer metal between the ferroelectric layer and metal–insulator–semiconductor structure. The metal interlayer averages out spatial variation in the ferroelectric polarization, enabling a compact charge‐based relation between the layers. In addition, the approach assumes that the NC effect emerges from the ferroelectric layer regardless of the metal interlayer, which is not necessarily probable. This work reinvestigates the possible NC effect in ferroelectric–dielectric capacitors connected by a metal interlayer. The experiment confirms that the NC effect in the metal–ferroelectric–dielectric–metal structure does not appear in the metal–ferroelectric–metal–dielectric–metal structure. These results are inconsistent with the multidomain‐1D Landau–Ginzburg‐Devonshire model. In contrast, the suppression of the NC effect in the structure is fully explained by the advanced inhomogeneous stray‐field energy model, which simulates the dynamic evolution of polarization and screening charges. Therefore, an NCFET with a metal interlayer is impractical.

Ferroelectric source follower for voltage-sensing nonvolatile memory and computing-in-memory

Abstract Memory arrays and computing-in-memory architecture based on emerging nonvolatile memory devices with a current-sensing scheme face several challenges when implemented in large-scale arrays, such as power and area penalties, voltage drop, and power-source limitations. Here, we demonstrate ferroelectric source followers as nonvolatile memory devices operating with a voltage-sensing scheme. The voltage output read out from the source terminal of a ferroelectric field-effect transistor is determined in a nonvolatile manner by the polarization state stored in a ferroelectric gate insulator, giving a higher output voltage at a lower threshold voltage. Device modeling reveals that the output voltage is described by a simple expression of the threshold voltage, gate bias, drain bias, and body-effect factor. Simple characteristics, low readout energy consumption (∼fJ) owing to an absence of steady current, and fast readout operation (∼ns) make ferroelectric source followers promising for voltage-sensing nonvolatile memory and voltage-sensing synapse as well as activation functions (biased rectified linear units) in computing-in-memory.

Memory and Synaptic Devices Based on Emerging 2D Ferroelectricity

AbstractMemory devices are an essential part of modern electronics. Efforts to move beyond the traditional “read” and “write” of digital information in volatile and non‐volatile memory devices are leading to the rapid growth of neuromorphic technology. There is a growing demand for memory devices with continuous memory states with various retention times and greater integration density with more energy‐efficient mechanisms. Two types of memory devices (i.e., non‐volatile digital memory and neuro‐synaptic devices) have been extensively investigated with emerging materials. Among numerous materials for such memory devices, in this review, the authors focus on 2D ferroelectric materials for promising memory and synaptic devices. Three types of memory devices based on 2D ferroelectric materials are classified and discussed here: 1) ferroelectric gating of semiconducting channels, 2) active ferroelectric channels, and 3) ferroelectric tunnel junction devices. It is known that atomically thin geometry competes with ferroelectricity, which can degrade the quality of the devices based on atomically thin ferroelectric materials. Various efforts to resolve the fundamental issue with emerging 2D ferroelectric materials and how they can be used as a critical element for memory and synaptic devices are surveyed.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

Recent Progress of E‐mode Gallium Nitride Metal–Insulator–Semiconductor ‐High Electron Mobility Transistors with Hybrid Ferroelectric Charge Trap Gate (FEG‐HEMT) for Power Switching Applications

Aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure devices have proven to be highly effective for high‐frequency power amplifiers and power switching applications with improved performance compared to those made with traditional silicon technology and other advanced semiconductor technologies. The development of enhancement‐mode (E‐mode) AlGaN/GaN high electron mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS‐HEMTs) has been a focus in recent years due to their potential applications. Arising from the concept of a flash‐memory‐like hybrid ferroelectric charge storage structure, the high‐performance hybrid ferroelectric charge storage gate (FEG) GaN HEMT has gradually gained a great deal of attention due to the concept being a useful and versatile tool to realize E‐mode operations. This article attempts to review the latest progresses in this technology, including alternative improvements and device characteristics. Future challenges for the E‐mode FEG‐HEMT are also discussed.

Bending Stability of Ferroelectric Gated Graphene Field Effect Transistor for Flexible Electronics.

In this work, we explored the potential of the ferroelectric gate of (Pb0.92La0.08)(Zr0.30Ti0.70)O3 (PLZT(8/30/70)) for flexible graphene field effect transistor (GFET) devices. Based on the deep understanding of the VDirac of PLZT(8/30/70) gate GFET, which determines the application of the flexible GFET devices, the polarization mechanisms of PLZT(8/30/70) under bending deformation were analyzed. It was found that both flexoelectric polarization and piezoelectric polarization exist under bending deformation, and their polarization direction is opposite under the same bending deformation. Thus, a relatively stable of VDirac is obtained due to the combination of these two effects. In contrast to the relatively good linear movement of VDirac under bending deformation of relaxor ferroelectric (Pb0.92La0.08)(Zr0.52Ti0.48)O3 (PLZT(8/52/48)) gated GFET, these stable properties of the PLZT(8/30/70) gate GFETs make them have great potential for applications in flexible devices.

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with metal/ferroelectric/interlayer/Si (MFIS) gate stack structure. In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect, we first establish a model to simulate the electron trapping behavior in n-type Si FeFET. The model is based on the quantum mechanical electron tunneling theory. And then, we use the pulsed I d–V g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET. Our model fits the experimental data well. By fitting the model with the experimental data, we get the following conclusions. (i) During the positive operation pulse, electrons in the Si substrate are mainly trapped at the interface between the ferroelectric (FE) layer and interlayer (IL) of the FeFET gate stack by inelastic trap-assisted tunneling. (ii) Based on our model, we can get the number of electrons trapped into the gate stack during the positive operation pulse. (iii) The model can be used to evaluate trap parameters, which will help us to further understand the fatigue mechanism of FeFET.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Ferroelectric Tunnel Thin-Film Transistor for Synaptic Applications

In this work, a ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrOx gate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ∼0.032 times in transfer characteristics and maximum conductance (Gd) of ∼ 0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate Gd, and it was found that using a pulse width of 75 ns could achieve low asymmetry ∼ 1 and high Gd ratio ∼ 20.63 under the consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the Gd ratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.