Ferroelectric Gate Research Articles

Improved lateral figure-of-merit of heteroepitaxial α-Ga2O3 power MOSFET using ferroelectric AlScN gate stack

In this Letter, we demonstrate heteroepitaxial α-Ga2O3 MOSFETs using an aluminum scandium nitride (AlScN) ferroelectric gate stack. Owing to ferroelectric effects, α-Ga2O3 MOSFETs with the AlScN/HfO2 gate stack (FGFET) exhibited enhanced electrical performance compared with a HfO2 gate dielectric (IGFET) for variable gate–drain lengths (10, 15, 20 μm). A remnant polarization value of the AlScN deposited on a HfO2 layer was measured to be about 30 μC/cm2. The subthreshold swing (SS) and field-effect mobility (μFE) of IGFET was extracted at 1814 mV/dec and 13.9 cm2/V s, respectively. However, the FGFET exhibits a reduced SS of 552 mV/dec with enhanced μFE of 42.7 cm2/V s owing to the negative capacitance of the ferroelectric AlScN. Furthermore, a lateral figure-of-merit of 17.8 MW/cm2 was achieved for the FGFET, far surpassing the 8.3 MW/cm2 of the IGFET. The proposed ferroelectric AlScN/HfO2 stack can be a promising gate structure for improving both transfer and breakdown characteristics in heteroepitaxial α-Ga2O3 power devices.

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain & gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.

New paradigms of 2D layered material self-driven photodetectors.

By virtue of the high carrier mobility, diverse electronic band structures, excellent electrostatic tunability, easy integration, and strong light-harvesting capability, 2D layered materials (2DLMs) have emerged as compelling contenders in the realm of photodetection and ushered in a new era of optoelectronic industry. In contrast to powered devices, self-driven photodetectors boast a wealth of advantages, notably low dark current, superior signal-to-noise ratio, low energy consumption, and exceptional compactness. Nevertheless, the construction of self-driven 2DLM photodetectors based on traditional p-n, homo-type, or Schottky heterojunctions, predominantly adopting a vertical configuration, confronts insurmountable dilemmas such as intricate fabrication procedures, sophisticated equipment, and formidable interface issues. In recent years, worldwide researchers have been devoted to pursuing exceptional strategies aimed at achieving the self-driven characteristics. This comprehensive review offers a methodical survey of the emergent paradigms toward self-driven photodetectors constructed from 2DLMs. Firstly, the burgeoning approaches employed to realize diverse self-driven 2DLM photodetectors are compiled, encompassing strategies such as strain modulation, thickness tailoring, structural engineering, asymmetric ferroelectric gating, asymmetric contacts (including work function, contact length, and contact area), ferroelectricity-enabled bulk photovoltaic effect, asymmetric optical antennas, among others, with a keen eye on the fundamental physical mechanisms that underpin them. Subsequently, the prevalent challenges within this research landscape are outlined, and the corresponding potential approaches for overcoming these obstacles are proposed. On the whole, this review highlights new device engineering avenues for the implementation of bias-free, high-performance, and highly integrated 2DLM optoelectronic devices.

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 μm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

Impact of ambient moisture on gate controllability in ferroelectric-gate field-effect transistors with bottom-gate geometry

Ferroelectric-gate field-effect transistors (FeFETs) with a bottom-gate geometry consisting of a ferroelectric HfO2 gate and an oxide channel have been intensively studied in recent years. However, there has been no detailed investigation into the impact of atmospheric exposure on device performance, even though the channel is often exposed to ambient air for process simplification, especially at the research stage. In this study, the ambient stability of an indium tin oxide channel FeFET with a ferroelectric Ce-HfO2 bottom gate was investigated. We found that ambient degradation of the gate controllability was caused by an increase in physisorbed water in the device owing to the intrusion of moisture. Mobile ions, such as H+, which can easily move through a network of hydrogen bonds formed by adjacent physisorbed water, may compensate for ferroelectric polarization. Finally, we demonstrated that the observed degradation can be managed effectively without compromising the original device characteristics using Al2O3 passivation gently formed via plasma-free deposition.

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance

We introduce two novel III-V inverted T-channel vertical line tunnel field-effect transistor (TFET) configurations, leveraging staggered bandgap compound materials. Design D-1 operate s without negative capacitance, while Design D-2 incorporates negative capacitance. Both designs employ area-enhanced gate normal line tunneling with dual-gate impact, utilizing InGaAs and GaAsSb materials to effectively reduce the overall bandgap. The double-area line tunneling, facilitated by the double gate, significantly enhances performance. D-1 exhibits notable improvements, with an ION value reaching 596.55 μA/μm, an ION/IOFF ratio of 2.5 × 108, a minimum subthreshold swing (SS) of 9.75 mV/dec, and an average subthreshold swing (AVSS) of 31.93 mV/dec. Building upon these achievements, D-2 takes a step further by implementing NC through a ferroelectric layer gate stack, significantly increasing the line tunneling rate symmetrically on the left and right channels beneath both gates. This marks the first proposal of double gate area-enhanced line tunneling with negative capacitance in this paper. D-2 demonstrates remarkable performance for future low-power applications.

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

Solution-processable low-voltage carbon nanotube field-effect transistors with high-k relaxor ferroelectric polymer gate insulator

Achieving energy-efficient and high-performance field-effect transistors (FETs) is one of the most important goals for future electronic devices. This paper reports semiconducting single-walled carbon nanotube FETs (s-SWNT-FETs) with an optimized high-k relaxor ferroelectric insulator P(VDF-TrFE-CFE) thickness for low-voltage operation. The s-SWNT-FETs with an optimized thickness (∼800 nm) of the high-k insulator exhibited the highest average mobility of 14.4 cm2 V−1s−1 at the drain voltage (I D) of 1 V, with a high current on/off ratio (I on/off >105). The optimized device performance resulted from the suppressed gate leakage current (I G) and a sufficiently large capacitance (>50 nF cm−2) of the insulating layer. Despite the extremely high capacitance (>100 nF cm−2) of the insulating layer, an insufficient thickness (<450 nm) induces a high I G, leading to reduced I D and mobility of s-SWNT-FETs. Conversely, an overly thick insulator (>1200 nm) cannot introduce sufficient capacitance, resulting in limited device performance. The large capacitance and sufficient breakdown voltage of the insulating layer with an appropriate thickness significantly improved p-type performance. However, a reduced n-type performance was observed owing to the increased electron trap density caused by fluorine proportional to the insulator thickness. Hence, precise control of the insulator thickness is crucial for achieving low-voltage operation with enhanced s-SWNT-FET performance.

Fabrication and characterization of HfxAl(1-x)Oy ceramic targets and thin films by RF sputtering

The potential of HfO2 as a memory semiconductor material with ferroelectric properties in thin-film deposition has been recently analyzed. In this study, the preparation, composition, and physical properties of Al-doped hafnium oxides were analyzed. HfxAl(1-x)Oy (HAO) [x = 0.33, 0.5, and 0.67] powders were prepared by controlling the ratio of Hf to Al and using ball milling. The HAO powder was calcined at 1000 °C in a furnace and then sintered in a temperature range of 1000–1600 °C by a solid-state reaction method to fabricate high-quality targets with high densities. The density and crystal size increased with the sintering temperature. The 1600-°C Hf0.67Al0.33Oy target was optimal for thin-film deposition. In addition, the target properties were affected by an increase in the HfO2 content x. The crystal structures and sizes, surface free energies, contact angles, and band gaps of the HAOs were evaluated to analyze their potential as high-k dielectric materials. HAO is a promising high-k dielectric and memory material, valuable for further studies on ferroelectric gate oxide materials. This study contributes to the increasing number of studies on the ferroelectricity of HfO2 thin films and provides a fundamental understanding of this material and its potential for novel device applications.

BCl3/Cl2 plasma etching process to fabricate a ferroelectric gate structure for device integration

Despite the significant potential of ferroelectric devices in overcoming the challenges faced by conventional high-k-based CMOS devices owing to the scaling of CMOS processes, most ferroelectric devices are not implemented in practical circuits yet. For practical application, integrating them into a circuit is essential, and the development of a reliable etching process is crucial for the integration of individual devices into circuits. Therefore, this study proposes a process for etching hafnium zirconium oxide (HZO)-based gate stacks to fabricate a gate structure and integrate HZO-based devices into circuits. First, poly-Si/TiN/HZO/TiN/SiO2 was deposited on a Si substrate and etched via Cl2 and BCl3/Cl2 plasma etchings. Cl2 plasma etching was found to be less effective, whereas BCl3/Cl2 plasma etching exhibited a higher etching rate. The optimal etching time for the BCl3/Cl2 plasma at which the entire stack was successfully removed was 50 s. Furthermore, the optimal ratio of Ar:Cl2:BCl3 that resulted in minimal damage to the Si surface was determined to be 1:1:3. These results led to the successful formation of an HZO-based gate structure and provided the potential to integrate ferroelectric devices into the circuit, thereby enabling their practical utilization.

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

Ambipolar MoS2 Field Effect Transistors with Negative Photoconductivity and High Responsivity Using an Ultrathin Epitaxial Ferroelectric Gate

AbstractFerroelectric field effect transistors (FeFETs), characterized by their low power consumption and polarization effect, can be employed in photodetectors based on 2D materials. In this paper, a MoS2 phototransistor with epitaxial ferroelectric (Hf0.5Zr0.5)O2 (HZO) is reported as a gate dielectric layer. Gate‐dielectric‐polarization‐dependent ambipolar behavior is observed in the FET, and relatively low power consumption and hysteresis‐free loop are achieved in the FeFET. The anomalous negative photoconductivity (NPC) is observed as well. Possible reasons for such phenomenon are clarified including the photogating effect originating from the interface traps and the polarization‐dependent electric‐field control through ferroelectric gating. The high responsivity of −8.44 × 103 A W−1 in the negative photoconductivity as well as the response time of 500 ms are reported. The demonstrated Molybdenum disulfide (MoS2) FeFET photodetectors show great potential in the on‐chip complementary metal‐oxide semiconductor (CMOS)‐compatible circuits for multifunctional devices.

Ferroelectric Gate Enabled Programmable Photovoltaics in vdWHs for Self-Powered In-Memory Logics

Ferroelectric Gate Enabled Programmable Photovoltaics in vdWHs for Self-Powered In-Memory Logics

Polarizable Nonvolatile Ferroelectric Gating in Monolayer MoS2 Phototransistors.

Given the requirements for power and dimension scaling, modulating channel transport properties using high gate bias is unfavorable due to the introduction of severe leakages and large power dissipation. Hence, this work presents an ultrathin phototransistor with chemical-vapor-deposition-grown monolayer MoS2 as the channel and a 10.2 nm thick Al:HfO2 ferroelectric film as the dielectric. The proposed device is meticulously modulated utilizing an Al:HfO2 nanofilm, which passivates traps and suppresses charge Coulomb scattering with Al doping, efficiently improving carrier transport and inhibiting leakage current. Furthermore, a bipolar pulses excitable polarization method is developed to induce a nonvolatile electrostatic field. The MoS2 channel is fully depleted by the switchable and stable floating gate originating from remanent polarization, leading to a high detectivity of 2.05 × 1011 Jones per nanometer of gating layer (Jones nm-1) and photocurrent on/off ratio >104 nm-1, which are superior to the state-of-the-art phototransistors based on two-dimensional (2D) materials and ferroelectrics. The proposed polarizable nonvolatile ferroelectric gating in a monolayer MoS2 phototransistor promises a potential route toward ultrasensitive photodetectors with low power consumption that boast of high levels of integration.

Artificial Optoelectronic Synapses Based on Light‐Controllable Ferroelectric Semiconductor Memristor

AbstractNumerous synaptic devices have been explored for the next generation of energy‐efficient computing techniques. Among them, optoelectronic synaptic devices based on semiconductor/ferroelectric heterostructures have received a lot of attention lately due to their amazing parallelism, efficiency, and fault tolerance properties. However, polarizing the ferroelectric layer or gating the dielectric layer is necessary to achieve tunable synaptic functions, which generally causes an increase in energy consumption and complex manufacturing processes. Here, a simple and efficient method is demonstrated to develop a tunable optoelectronic synaptic device based on a single ferroelectric semiconductor, BiFeO3‐BaTiO3 (BF‐BT). Multi‐essential synaptic functions including short‐term plasticity, paired‐pulse facilitation, and long‐term plasticity are all satisfactorily replicated by the memristor device. More significantly, light‐controllable synaptic behaviors are realized by altering the ferroelectric polarization state of BF‐BT. Synaptic devices’ relaxation characteristics enable simulation of the effects of positive/negative emotions on learning and forgetting processes. This study highlights the potential of the ferroelectric semiconductor memristor in constructing the efficient optoelectronic synapses for future neuromorphic electronics with the ability to learn and sense optical information.

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor.

In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source-channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (qf), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (Id), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors' sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

Understanding memory window of ferroelectric field-effect transistor under coexistence of charge trapping and ferroelectric polarization: violation of linear superposition

Ferroelectric FETs (FeFETs) are nonvolatile memory devices in which the threshold voltage is programmed by the polarization state of the ferroelectric gate insulator. In this study, we theoretically investigate the impact of charge trapping on the ferroelectric memory window by establishing an accurate picture of mechanism determining the threshold voltage. Under the co-existence of ferroelectric polarization and charge trapping, we show that the threshold voltage shift cannot be described by the linear superposition of the ferroelectric-polarization component and the charge-trapping component. We point out that the misuse of the linear superposition can significantly underestimate the trapped charge density in FeFETs, sometimes even by an order of magnitude. The concept of effective dielectric constant determined by both the original dielectric constant and the polarization state is discussed to describe the relation between the threshold voltage shift and trapped charge density in FeFETs.

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).