Ferroelectric Field-effect Transistors Research Articles

Impact of multi-domain effect on the effective carrier mobility of ferroelectric field-effect transistor

HfO2-based ferroelectric field-effect transistors (FeFETs) are a promising candidate for multilevel memory manipulation and brain-like computing due to the multi-domain properties of the HfO2 FE films based polycrystalline structure. Although there have been many reports on the working mechanism of the HfO2-based FeFET and improving its reliability, the impact of multi-domain effect on the effective carrier mobility (μ channel) has not been carried out yet. The effective μ channel determines the level of readout current and affects the accuracy of the precision of peripheral circuit. In this work, FeFETs with HfZrO x FE gate dielectric were fabricated, and the effect of write (or erase) pulses with linear gradient variation on the effective μ channel was studied. For the multiple downward polarization under write pulses, the μ channel degrades as the domains gradually switch to downward. This is mainly due to the enhancement of the scattering effect induced by the positive charges (e.g. oxygen vacancies ) trapping and the increase of channel carrier density. For the erase pulses, the μ channel increases as the domains gradually reverse to upward, which is mainly due to the reduction of the scattering effect induced by the detrapping of positive charges and the decrease of channel carrier density. In addition, the modulation effect of multilevel polarization states on μ channel is verified by numerical simulation. This effect provides a new idea and solution for the development of low power HfO2-based FeFETs in neuromorphic computing.

Embedding security into ferroelectric FET array via in situ memory operation

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

A Comparative Study of n- and p-Channel FeFETs with Ferroelectric HZO Gate Dielectric

This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs.

Asymmetric conducting route and potential redistribution determine the polarization-dependent conductivity in layered ferroelectrics.

Precise control of the conductivity of layered ferroelectric semiconductors is required to make these materials suitable for advanced transistor, memory and logic circuits. Although proof-of-principle devices based on layered ferroelectrics have been demonstrated, it remains unclear how the polarization inversion induces conductivity changes. Therefore, function design and performance optimization remain cumbersome. Here we combine ab initio calculations with transport experiments to unveil the mechanism underlying the polarization-dependent conductivity in ferroelectric channel field-effect transistors. We find that the built-in electric field gives rise to an asymmetric conducting route formed by the hidden Stark effect and competes with the potential redistribution caused by the external field of the gate. Furthermore, leveraging our mechanistic findings, we control the conductivity threshold in α-In2Se3 ferroelectric channel field-effect transistors. We demonstrate logic-in-memory functionality through the implementation of electrically self-switchable primary (AND, OR) and composite (XOR, NOR, NAND) logic gates. Our work provides mechanistic insights into conductivity modulation in a broad class of layered ferroelectrics, providing foundations for their application in logic and memory electronics.

Integrated In-Memory Sensor and Computing of Artificial Vision Based on Full-vdW Optoelectronic Ferroelectric Field-Effect Transistor.

The development and application of artificial intelligence have led to the exploitation of low-power and compact intelligent information-processing systems integrated with sensing, memory, and neuromorphic computing functions. The 2D van der Waals (vdW) materials with abundant reservoirs for arbitrary stacking based on functions and enabling continued device downscaling offer an attractive alternative for continuously promoting artificial intelligence. In this study, full 2D SnS2 /h-BN/CuInP2 S6 (CIPS)-based ferroelectric field-effect transistors (Fe-FETs) and utilized light-induced ferroelectric polarization reversal to achieve excellent memory properties and multi-functional sensing-memory-computing vision simulations are designed. The device exhibits a high on/off current ratio of over 105 , long retention time (>104 s), stable cyclic endurance (>350 cycles), and 128 multilevel current states (7-bit). In addition, fundamental synaptic plasticity characteristics are emulated including paired-pulse facilitation (PPF), short-term plasticity (STP), long-term plasticity (LTP), long-term potentiation, and long-term depression. A ferroelectric optoelectronic reservoir computing system for the Modified National Institute of Standards and Technology (MNIST) handwritten digital recognition achieved a high accuracy of 93.62%. Furthermore, retina-like light adaptation and Pavlovian conditioning are successfully mimicked. These results provide a strategy for developing a multilevel memory and novel neuromorphic vision systems with integrated sensing-memory-processing.

An analytical interpretation of the memory window in ferroelectric field-effect transistors

In this study, we present an analytical equation for describing the memory window of ferroelectric field-effect transistors (FeFETs). The analytical equation is derived based on the effect of oxide charge on the threshold voltage shift of the field-effect transistor and can be expressed by simpler parameters, such as the quantity of polarization switching and trapped charge. We demonstrate that the derived equation is in quantitative agreement with the results of the numerical calculations using a technology computer-aided design simulation tool, which confirms the validity of the equation. Our results show that the analytical equations provide an accurate and practical description of the memory window for FeFETs with various structures.

ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories

Ferroelectric Field Effect Transistors (FeFETs) have spurred increasing interest in both memories and computing applications, thanks to their CMOS compatibility, low-power operation, and high scalability. However, new security threats to the FeFET-based memories also arise. A major threat is the power analysis side-channel attack (P-SCA), which exploits the power traces of the memory access to obtain data information. There have been several effective efforts on resistive nonvolatile memories (NVMs), but they fail to meet the requirements for secure FeFET-based memories due to the different capacitive FeFETs load. Directly applying these existing countermeasures to the P-SCA protection for FeFETs induces huge challenges, especially for the balance between power side-channel resistance and corresponding overheads. To address this issue, we leverage the unique features of FeFETs and propose ProtFe , namely the protection methods for FeFET-based memories, including the pipelined multi-step write strategy ( PiMWrite ) and the split array design ( SpA ). PiMWrite is proposed for general FeFET-based memories, and inserts specially designed intermediate states to mitigate information leakage with pipelined steps to reduce overheads. SpA is proposed for custom FeFET-based memories, and simultaneously writes two split portions of the array with shared minimized peripherals to go beyond the balance between security and overheads. Simulation results show that PiMWrite expands the search space of a single power trace to 21× and involves nearly zero hardware penalties. SpA presents 33× search space improvement with negligible latency, 0.6% area, and only 7.1% energy overhead. ProtFe achieves improved balance between security and overheads, compared with the state-of-the-art works.

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Unraveling the effect of pressure on structural phase transition, electronic, and optical properties of Hf1-xSixO2 (x = 0, 0.03, 0.06, 0.09): A first-principles investigation

The non-centrosymmetric phase of HfO2 with excellent Si compatibility has great importance in integrated photonic circuits, non-volatile memory, and ferroelectric field effect transistors. We report a theoretical study of pressure-induced phase transition from a centrosymmetric m-HfO2 to non-centrosymmetric o-HfO2 with Si doping. The reported phase transition pressures, i.e. 15, 14, 8, and 8 GPa for x = 0, 0.03, 0.06, and 0.09, respectively, for Hf1-xSixO2 are in excellent agreement with available experimental results. With increasing Si concentrations, the transition pressures reduce significantly, which is explained in terms of bond length and charge transfer. The thermal stability of the obtained o-HfO2 phase is examined via ab-initio molecular dynamics up to its synthesis temperature. The negative formation energy also confirms its thermodynamical stability. Density of states indicates the noticeable appearance of Si states in the lower conduction band and an increase in the extent of hybridization between Hf-5d, O-2p, and Si-2p atomic states. The doping changes the nature of band gap from indirect to direct, concurrently reducing the magnitude. The o-HfO2 shows a low value of static dielectric constant, which results in a smaller refractive index (1.82) and lower reflectivity in the infrared and visible regions.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

FeFET-Based In-Memory Hyperdimensional Encoding Design

The data explosion of Internet-of-Things (IoTs) and machine learning tasks raises a great demand on highly efficient computing hardware and paradigms. Brain-inspired hyperdimensional computing (HDC) is becoming a promising computing paradigm, which encodes data as hypervectors with homogeneous elements instead of numbers, and can perform learning/classification tasks through simple logical or arithmetic operations on the encoded hypervectors. Therefore HDC has much lower computational complexity than conventional computational models such as neural networks. However, due to its high-dimensional data representation, processing and encoding hypervectors in conventional Von-Neumann architectures (e.g., CPU and GPU) requires a large amount of energy-and time-consuming data transfer, thus weakening its efficiency benefiting from low complexity. In this paper, we proposed an ultra-low power and fast computing-in-Memory (CiM) design based on non-volatile (NV) Ferroelectric FET (FeFET) for HDC encoding. The proposed design mainly support hyperdimensional bit-wise XOR and parallel majority vote (MAJ) operations for HDC encoding, which are implemented by FeFET based memories together with CMOS peripheral circuits. The 1FeFET1T based memory cell effectively mitigates the impact of transistor variations on the operation. A highly parallel and pipelined computing workflow of the proposed design further boosts the energy efficiency and performance with negligible extra area overhead. Experimental results demonstrate that our proposed design achieves 5.04× energy efficiency improvement over other CiM designs for HDC encoding.

Impacts of Zr content of HfZrOx-Based FeFET memory on resilience towards proton radiation

High energy/fluence (10 MeV/2.5 × 1014 ions·cm−2) proton radiation effects on the performance of HfZrOx (HZO)-based ferroelectric field effect transistors (FeFETs) memory with various Zr content were studied for the first time. As the Zr content reaches 67 % (tetragonal-phase rich), degraded de-trapping, switching speed, memory window (MW) and polarization-voltage slope occur due to more oxygen vacancies (Vo) generation upon proton radiation resulting from intrinsically higher amount Vo. For FeFETs (Zr: 50 %), irradiated devices exhibit a MW of ∼ 2.4 V while other characteristics show almost independent of radiation. The irradiated FeFETs also reveal good endurance up to 109 cycles by recovery and 10-year retention. The higher resilience towards radiation for FeFETs (Zr: 50 %) is obtained since Vo redistribution is dominant with negligible Vo generation, making it eligible for space missions.

Negative capacitance field-effect transistors based on ferroelectric AlScN and 2D MoS2

Al0.68Sc0.32N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory applications have been demonstrated, a device for logic applications with minimal hysteresis has not been reported. This study reports on the transport characteristics of a MoS2 negative capacitance FET (NCFET) based on an AlScN ferroelectric material. We experimentally demonstrate the effect of a dielectric layer in the gate stack on the memory window and subthreshold swing (SS) of the NCFET. We show that the hysteresis behavior of transfer characteristics in the NCFET can be minimized with the inclusion of a non-ferroelectric dielectric layer, which fulfills the capacitance-matching condition. Remarkably, we also observe the NC effect in MoS2/AlScN NCFETs arrays based on large-area monolayer MoS2 synthesized by chemical vapor deposition, showing the SS values smaller than its thermionic limit (∼36 to 60 mV/dec) and minimal variation in threshold voltages (<20 mV).

Two-dimensional van der Waals ferroelectric field-effect transistors toward nonvolatile memory and neuromorphic computing

With the gradual decline in Moore's law, traditional silicon-based technologies have encountered numerous challenges and limitations, prompting researchers to seek solutions. Two-dimensional (2D) van der Waals (vdWs) ferroelectric (Fe) field-effect transistors (FETs) (2D vdWs FeFETs) are devices that integrate emerging 2D vdWs ferroelectric materials into the transistor structures. In comparison with traditional complementary metal oxide semiconductor FETs (COMSFETs), they exhibit superior performance, including lower power consumption, higher switching speed, and improved stability. The vdWs FeFETs are anticipated to surpass the limits imposed by Moore's law, offering increased possibilities and opportunities for research and application in the field of nanoelectronics, particularly in nonvolatile memory (NVM) and neuromorphic computing (NMC). In this review, we summarize the recent research progress of vdWs FeFETs and elucidate their development origin, basic structure, and working mechanism. Furthermore, we explore the application of vdWs FeFETs in NVM, NMC, and large-scale arrays. Finally, we highlight the prominent challenges and future directions in this field.

Artificial Visual Systems Fabricated with Ferroelectric van der Waals Heterostructure for In-Memory Computing Applications.

Rapid developments in artificial neural network techniques and retina-inspired artificial visual systems are required to realize the sensing, processing, and memorization of an optical signal in a single device. Herein, a ferroelectric field-effect transistor fabricated with CuInP2S6 and α-In2Se3 van der Waals heterostructures is proposed and demonstrated for the development of an artificial visual system. The dipole polarizations are coupled and bidirectionally locked inside the ferroelectric α-In2Se3 along the in-plane and out-of-plane directions and are controlled by the gate voltages. Furthermore, light-induced polarization can change the order of polarization of the dipoles inside α-In2Se3. We demonstrate that using the combined control of these electrical and optical signals, the device may function like a retina-inspired vision system. The device can operate across a wide wavelength range (405-850 nm) and detect very low incident light (0.03 mW/cm2). Color recognition, high paired-pulse facilitation (∼170%), and short- to long-term memory transitions through quick learning are observed using this device. Additionally, this device demonstrates different complex processing abilities, including pattern recognition, light adaptation, optical logic operation, and event learning. The proposed ferroelectric heterostructure-based artificial visual system can serve as an essential bridge for fulfilling the future requirements of all-in-one sensing and memory-processing devices.

Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3 for stacked in-memory computing array

In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfer. Nevertheless, it necessitates a high-density memory array to effectively manage large data volumes. Here, we present a stacked ferroelectric memory array comprised of laterally gated ferroelectric field-effect transistors (LG-FeFETs). The interlocking effect of the α-In2Se3 is utilized to regulate the channel conductance. Our study examined the distinctive characteristics of the LG-FeFET, such as a notably wide memory window, effective ferroelectric switching, long retention time (over 3 × 104 seconds), and high endurance (over 105 cycles). This device is also well-suited for implementing vertically stacked structures because decreasing its height can help mitigate the challenges associated with the integration process. We devised a 3D stacked structure using the LG-FeFET and verified its feasibility by performing multiply-accumulate (MAC) operations in a two-tier stacked memory configuration.

Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic Circuits.

Emerging reconfigurable devices are fast gaining popularity in the search for next-generation computing hardware, while ferroelectric engineering of the doping state in semiconductor materials has the potential to offer alternatives to traditional von-Neumann architecture. In this work, we combine these concepts and demonstrate the suitability of reconfigurable ferroelectric field-effect transistors (Re-FeFETs) for designing nonvolatile reconfigurable logic-in-memory circuits with multifunctional capabilities. Modulation of the energy landscape within a homojunction of a 2D tungsten diselenide (WSe2) layer is achieved by independently controlling two split-gate electrodes made of a ferroelectric 2D copper indium thiophosphate (CuInP2S6) layer. Controlling the state encoded in the program gate enables switching between p, n, and ambipolar FeFET operating modes. The transistors exhibit on-off ratios exceeding 106 and hysteresis windows of up to 10 V width. The homojunction can change from Ohmic-like to diode behavior with a large rectification ratio of 104. When programmed in the diode mode, the large built-in p-n junction electric field enables efficient separation of photogenerated carriers, making the device attractive for energy-harvesting applications. The implementation of the Re-FeFET for reconfigurable logic functions shows how a circuit can be reconfigured to emulate either polymorphic ferroelectric NAND/AND logic-in-memory or electronic XNOR logic with a long retention time exceeding 104 s. We also illustrate how a circuit design made of just two Re-FeFETs exhibits high logic expressivity with reconfigurability at runtime to implement several key nonvolatile 2-input logic functions. Moreover, the Re-FeFET circuit demonstrates high compactness, with an up to 80% reduction in transistor count compared to standard CMOS design. The 2D van de Waals Re-FeFET devices therefore exhibit promising potential for both More-than-Moore and beyond-Moore future of electronics, in particular for an energy-efficient implementation of in-memory computing and machine learning hardware, due to their multifunctionality and design compactness.

Low Operating Voltage and Immediate Read‐After‐Write of HZO‐Based Si Ferroelectric Field‐Effect Transistors with High Endurance and Retention Characteristics

AbstractThe study demonstrates HfZrOx (HZO)‐based Si ferroelectric field‐effect transistors (FeFETs) with a low operating voltage (1.5 V) and immediate read‐after‐write operation (100 ns) via HZO thickness scaling, electron‐beam‐irradiation (EBI) treatment, and interfacial layer (IL) scavenging. With these three strategies, reduced operating voltage, immediate read‐after‐write capability, and improved endurance (>108 cycles) and retention (extrapolated 10‐year) characteristics are achieved in FeFETs. The improved characteristics of FeFETs are attributed to the reduced operating voltage by HZO thickness scaling, the ferroelectric orthorhombic phase‐oriented crystallization by EBI treatment, and the reduced gate voltage drop across the IL and reduced depolarization field by the IL scavenging. It is believed that this work contributes to the development of low‐power and fast‐read FeFETs.

Observing suppressed polarization in flexible ferroelectric negative capacitance field effect transistors

Negative capacitance (NC) has the potential to enable low power microelectronics beyond the fundamental thermionic limit, and it has been theorized that the thermodynamically unstable NC of ferroelectrics can be stabilized by linear dielectric, making negative capacitance ferroelectric field effect transistors (NC-FeFET) possible. Nevertheless, the validity of NC as a physical concept for ferroelectrics remain contentious despite numerous theoretical and experimental investigations, and the intrinsic ferroelectric NC with suppressed polarization has not been demonstrated except locally at vortex core. While NC-FeFET with subthreshold swing (SS) lower than 60 mV/dec limit has been reported, such device characteristics has not been directly connected to suppressed polarization at materials’ level, and alternative mechanisms other than NC have also been proposed. Here we demonstrate stable sub-60 mV/dec SS with hysteresis free IV in NC-FeFET based on SrTiO3/Pb(Zr0.1Ti0.9)O3/SrTiO3 heterostructure, and observe its suppressed polarization at both macroscopic and microscopic scales. The intrinsic ferroelectric NC thus is experimentally confirmed and directly connected to NC-FeFET performance, and the mica-based device is also highly flexible and robust under cyclic bending as well as extended heating.