Ferroelectric Field-effect Transistors Research Articles

Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one.

Ultra-Low Voltage Schmitt Triggers Implemented by HfO2-Based Ferroelectric Field-Effect Transistors

In this letter, a simple ultra-low voltage Schmitt trigger is demonstrated. It consists of an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric field-effect transistor (FeFET) and a load transistor, which greatly simplifies the circuit design and reduces the power consumption in contrast with traditional Schmitt trigger with four to six transistors. The Schmitt trigger has two different threshold voltages without fluctuation at different supply voltages and it can still be operated even at 10 mV. Waveform transformation is successfully implemented through the Schmitt trigger and the output square waveform is obtained even with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 10 mV. The Schmitt trigger can also perform logic-state transition under input pulse with width down to 20 ns, which may be considered for the realization of logic-in-memory applications. This multifunctional device demonstrates advantages in simple circuits and low voltage, showing great potential in ultra-low power integrated circuit applications such as wearable systems and bio-implantable microcircuits.

FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors

Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature.

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

Asymmetric Ferroelectric-Gated Two-Dimensional Transistor Integrating Self-Rectifying Photoelectric Memory and Artificial Synapse.

Ferroelectric field-effect transistors (Fe-FET) are promising candidates for future information devices. However, they suffer from low endurance and short retention time, which retards the application of processing memory in the same physical processes. Here, inspired by the ferroelectric proximity effects, we design a reconfigurable two-dimensional (2D) MoS2 transistor featuring with asymmetric ferroelectric gate, exhibiting high memory and logic ability with a program/erase ratio of over 106 and a self-rectifying ratio of 103. Interestingly, the robust electric and optic cycling are obtained with a large switching ratio of 106 and nine distinct resistance states upon optical excitation with excellent nonvolatile characteristics. Meanwhile, the operation of memory mimics the synapse behavior in response to light spikes with different intensity and number. This design realizes an integration of robust processing memory in one single device, which demonstrates a considerable potential of an asymmetric ferroelectric gate in the development of Fe-FETs for logic processing and nonvolatile memory applications.

Effect of thickness scaling on the switching dynamics of ferroelectric HfO2–ZrO2 capacitors

HfO2-based ferroelectric (FE) films have attracted immense attention in the research of ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistors (FeFETs) due to their excellent ferroelectric performance and high compatibility with CMOS integration. The study of switching dynamics is essential in understanding and optimizing HfO2-based FE films for nonvolatile memory applications. To explore the effect of thickness scaling on the polarization switching speed of the HfO2-ZrO2 (HZO) FE film, we demonstrate TaN/HZO/TaN capacitors fabricated with 6, 10, and 20 nm-thick HZO films. The inhomogeneous field mechanism (IFM) model was used to characterize the polarization switching of polycrystalline HZO films. The results showed that the characteristic time constants for the 6, 10, and 20-nm-thick HZO samples were 283, 43.7, and 20.5 ps, respectively, which is inconsistent with the variation in coercive electric field (EC) with sample thickness. These results demonstrate the distribution of the local fields in capacitors with various HZO thicknesses and contribute to the design and optimization of HZO films for advanced nanonode applications.

Improvement in nonvolatile memory operations for metal–ferroelectric–insulator–semiconductor capacitors using HfZrO2 and ZrO2 thin films as ferroelectric and insulator layers

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were characterized to elucidate the optimum design schemes for the ferroelectric field-effect transistor applications. The Hf1−x Zr x O2 (HZO) thin films (18 nm) were prepared on the SiO2 and ZrO2 insulator layers (ILs) with different film thicknesses. The choice of 10 nm thick ZrO2 IL was found to be an optimum condition to properly balance between the values of electric fields applied to the HZO (E HZO) and ZrO2 (E IL) layers, leading to effective improvement in capacitance coupling ratio and to suppression of charge injection for the MFIS capacitors. Furthermore, the crystalline natures of the crystallized HZO films were also found to be strategically controlled on the ZrO2 ILs, which can additionally enhance the E HZO with reducing the E IL. As consequences, the MFIS capacitors using 10 nm thick ZrO2 IL exhibited the ferroelectric memory window as large as 2.5 V at an application of ±5 V, which corresponds to 2.7 times wider value, compared to that obtained from the device using 2 nm thick SiO2 IL. Long-time memory retention and robust program endurance were also verified for the fabricated MFIS capacitors.

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect

Compute-in-memory (CIM) paradigm using ferroelectric field effect transistor (FeFET) as the weight element is projected to exhibit excellent energy efficiency for accelerating deep neural network (DNN) inference. However, two challenges exist. On the technology level, the chip area scaling is stalled due to the lack of logic voltage compatible FeFET at leading-edge technology node, e. g. 7nm. On the system level, CIM-based inference engine designs are usually customized for a specific DNN model, lacking the flexibility to support different DNN models. Besides, communication latency varies across different DNN models and can bound the total inference latency. Therefore, a reconfigurable interconnect is desired to be adaptive to different workloads, which can induce high area cost due to the reconfigurable circuit modules. To solve these issues, in this work, a system-technology co-design (STCO) of a monolithic 3D (M3D) reconfigurable CIM accelerator is performed, where back-end-of-line (BEOL) compatible oxide channel MOSFET and FeFET technologies are utilized. On the technology level, W-doped indium oxide (IWO) NMOS is utilized to design area-efficient M3D write circuit. On the system level, a reconfigurable interconnect design that inserts workload-specific express link is proposed, where the IWO-based NMOS and FeFET are adopted as the building element of the mux and crossbar switch in the router. The algorithm for interconnect configuration is also devised to achieve optimal latency for different workloads. From the system-level evaluation results, M3D IWO FeFET design (utilizing a hybrid 22nm/7nm M3D partition) shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.1\times $ </tex-math></inline-formula> times higher energy efficiency than a 7nm 2D SRAM design with comparable chip area. With the proposed reconfigurable interconnect scheme, the interconnect latency is reduced by 9%~32% compared to the baseline with a regular mesh network.

Relatively Low-k Ferroelectric Nonvolatile Memory Using Fast Ramping Fast Cooling Annealing Process

Hafnia-based ferroelectric field-effect transistors (FeFETs) with low power, scalability, and nonvolatile switching can overcome the performance limitations of conventional von Neumann computing technology. However, achieving a large memory window and excellent endurance in FeFET devices composed of two capacitors, such as ferroelectric and interfacial insulator capacitors, remains a challenge due to the strong electric field applied to the insulator, which accounts for the low permittivity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> ) of interfacial insulator. In addition, write disturb (WD) is considered to be a hurdle in the practical array operation of 1T-type FeFET devices. In this study, we propose a core process in which the dielectric constant and grain size of hafnia ferroelectric are adjusted by the ramping/cooling process, achieving high speed (20 ns), high reliability (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> ), and negligible disturb (0 V in 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3{V}_{dd}$ </tex-math></inline-formula> operation) FeFET. This results from effective voltage drop and switching across a relatively low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> ferroelectric capacitor that is connected with an interfacial insulator. Intriguingly, using low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> HfZrO as a gate, the proposed 3-D structure FeFET exhibits an improved memory window and robustness in WD in the array operation. These results suggest an informative way to design a high memory performance of FeFETs for future applications.

How to process P(VDF-TrFE) thin films for controlling short circuits in flexible non-volatile memories

Severe electrical shorting is one of the biggest challenges for the development of flexible non-volatile ferroelectric memories with low operation voltage. In this work, short circuits in flexible ferroelectric capacitors based on copolymer poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)], were explicitly investigated. It was found that processing conditions of P(VDF-TrFE) films have huge effects on electrical shorting conditions. Both deciding factors such as drying temperatures, solvent evaporation rates, and solution concentrations, and plausible factors such as post-drying thermal annealing, were clearly identified. These deciding factors were found to affect short circuits by altering the film porosity, surface roughness, and defect conditions in P(VDF-TrFE) thin films. The detailed correlation of these factors with film porosity were established and explained within the framework of liquid-liquid phase separation. The correlation with the surface roughness and defect conditions were explained with Marangoni convection. The net effects of these factors on electrical shorting conditions are rather complicated because a favorable factor with regards to film porosity may be detrimental in terms of surface roughness and/or defects. So these factors have to been carefully tailored to control short circuits and generate high yields in P(VDF-TrFE) thin film memory devices. Comparative study shows that drying at 80 °C in open air is the optimal condition for processing P(VDF-TrFE) thin films from PGMEA solution. Under this optimal drying condition, a yield of 76% was achieved from large-area devices of about 200 μm × 200 μm with thin P(VDF-TrFE) films of about 200 nm processed with roll-2-roll compatible techniques on plastic substrates. An effective two-step approach to manufacturing P(VDF-TrFE) layers for ferroelectric capacitors with low operation voltage but high yields, is presented. The key information gained from this work on ferroelectric capacitors could be generalized to another type of ferroelectric memories, namely ferroelectric field effect transistors. So it provides researchers and engineers a general guideline on how to control short circuits by processing P(VDF-TrFE) thin films for flexible non-volatile memories.

Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture

Specialized hardware accelerators beyond von-Neumann, that offer processing capability in where the data resides without moving it, become inevitable in data-centric computing. Emerging non-volatile memories, like Ferroelectric Field-Effect Transistor (FeFET), are able to build compact Logic-in-Memory (LiM). In this work, we investigate the probability of error (Perror) in FeFET-based XNOR LiM, demonstrating the new trade-off between the speed and reliability. Using our reliability model, we present how Binarized Neural Networks (BNNs) can be proactively trained in the presence of XNOR-induced errors towards obtaining robust BNNs at the design time. Furthermore, leveraging the trade-off between Perror and speed, we present a run-time adaptation technique, that selectively trades-off Perror and XNOR speed for every BNN layer. Our results demonstrate that when a small loss (e.g., 1%) in inference accuracy could be accepted, our design-time and run-time techniques provide error-resilient BNNs that exhibit 75% and 50% (FashionMNIST) and 38% and 24% (CIFAR10) XNOR speedups, respectively.

A FeFET-Based Hybrid Memory Accessible by Content and by Address

Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.

Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation

The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. External tensile stress increases the memory window and off-state current, while compressive stress decreases it. This study shows that a ferroelectric topology can be used as memory and could significantly increase the storage density of ferroelectric memory.

Ferroelectric Field‐Effect‐Transistor Integrated with Ferroelectrics Heterostructure

To address the demands of emerging data‐centric computing applications, ferroelectric field‐effect transistors (Fe‐FETs) are considered the forefront of semiconductor electronics owing to their energy and area efficiency and merged logic–memory functionalities. Herein, the fabrication and application of an Fe‐FET, which is integrated with a van der Waals ferroelectrics heterostructure (CuInP2S6/α‐In2Se3), is reported. Leveraging enhanced polarization originating from the dipole coupling of CIPS and α‐In2Se3, the fabricated Fe‐FET exhibits a large memory window of 14.5 V at V GS = ±10 V, reaching a memory window to sweep range of ≈72%. Piezoelectric force microscopy measurements confirm the enhanced polarization‐induced wider hysteresis loop of the double‐stacked ferroelectrics compared to single ferroelectric layers. The Landau–Khalatnikov theory is extended to analyze the ferroelectric characteristics of a ferroelectric heterostructure, providing detailed explanations of the hysteresis behaviors and enhanced memory window formation. The fabricated Fe‐FET shows nonvolatile memory characteristics, with a high on/off current ratio of over 106, long retention time (>104 s), and stable cyclic endurance (>104 cycles). Furthermore, the applicability of the ferroelectrics heterostructure is investigated for artificial synapses and for hardware neural networks through training and inference simulation. These results provide a promising pathway for exploring low‐dimensional ferroelectronics.

Neural sampling machine with stochastic synapse allows brain-like learning and inference

Many real-world mission-critical applications require continual online learning from noisy data and real-time decision making with a defined confidence level. Brain-inspired probabilistic models of neural network can explicitly handle the uncertainty in data and allow adaptive learning on the fly. However, their implementation in a compact, low-power hardware remains a challenge. In this work, we introduce a novel hardware fabric that can implement a new class of stochastic neural network called Neural Sampling Machine (NSM) by exploiting the stochasticity in the synaptic connections for approximate Bayesian inference. We experimentally demonstrate an in silico hybrid stochastic synapse by pairing a ferroelectric field-effect transistor (FeFET)-based analog weight cell with a two-terminal stochastic selector element. We show that the stochastic switching characteristic of the selector between the insulator and the metallic states resembles the multiplicative synaptic noise of the NSM. We perform network-level simulations to highlight the salient features offered by the stochastic NSM such as performing autonomous weight normalization for continual online learning and Bayesian inferencing. We show that the stochastic NSM can not only perform highly accurate image classification with 98.25% accuracy on standard MNIST dataset, but also estimate the uncertainty in prediction (measured in terms of the entropy of prediction) when the digits of the MNIST dataset are rotated. Building such a probabilistic hardware platform that can support neuroscience inspired models can enhance the learning and inference capability of the current artificial intelligence (AI).

Detection of biomolecules in dielectric modulated double metal below ferroelectric layer FET with improved sensitivity.

In this work, we examined the double metal below ferroelectric layer FET that is double metal below negative capacitance field-effect transistor (DM-below-NCFET) for biosensing application and change in nanocavity gap with biomolecules as protein, {text{ChO}}_x (cholesterol oxidase), streptavidin, and uricase. For measuring the electrical characteristic and neutral biosensing such as threshold voltage, switching ratio (I_{text{on}}/I_{text{off}}) of the device which is higher than one without molecules by 1.52 times, sensitivity of protein enhanced by 1.11 over without biomolecule, limit of detection of protein is higher by 1.012 times over without molecule, shift in potential have been researched for cavity length 10 nm. The biosensor indicated improved sensitivity for biomolecules with the rise in their dielectric parameter. Moreover, modulation of the length of the gap of cavity was too examined, exposing that its increment (from 8 to 12 nm) altogether upgraded the sensitivity of the proposed biosensor. Visual TCAD (Technology Computer-Aided Design) software is used for simulating all results. In general, the consequences of this examination represent that such DM-below-NCFET biosensors can display extreme sensitivity (1.11) at small drain voltage (0.4 V), empowering their utilization for biosensor applications to analyze different infections which involve low power, extreme density, and enhanced speed.

Comparison of 2-D MoS2 and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability

This brief investigates scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs.

Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs

Ferroelectric field-effect transistors (FeFETs) based on HfO₂ are promising for low-power and high-speed non-volatile memory devices. However, most reported FeFETs show limited write endurance and significant read-after-write delay due to parasitic charge trapping. Here we show that n-type FeFETs with SiN_<i>x</i> interfacial layer and high write endurance also exhibit immediate read-after-write behavior due to negligible charge trapping. This overcomes one of the major challenges faced by FeFET technologies today.

Ultra-Efficient and Robust Auto-Nonvolatile Schmitt Trigger-Based Latch Design Using Ferroelectric CNTFET Technology.

In designing ultra-efficient noise immune nanoscale circuits and systems, Schmitt triggers (STs) are vital components influencing total functionality. This article proposes an ultracompact ST using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs) and a robust ST latch. By using the unique electrical futures of the Fe-CNTFETs, the proposed ST has been designed in a particular way to only employ two transistors similar to a conventional binary inverter. Moreover, by utilizing the negative capacitance feature of the Fe-CNTFETs, the proposed ST can perform the backup and restore operation during a scheduled power gating or a sudden power outage without imposing any additional transistors, interconnects, and control signals. The proposed ST latch is hardened to soft errors occurring due to unwanted single-event upsets (SEUs). Our extensive simulations demonstrate that our proposed ST latch offers lower transistors counts (on average 34%) and more energy savings (on average 79%). On the other hand, our design has shown 5.6 times on average higher critical charge tolerance than the previous counterparts due to its soft error hardening circuity and the superior hysteresis behavior of the proposed Fe-CNTFET-based ST. Moreover, the auto-nonvolatility of the proposed ST makes the proposed latches immune to the sudden power outage, which was not devised in the previous ST latches. Our results show new pathways in designing ultracompact and efficient nonvolatile ST latches using the Fe-CNTFET technology.

Review of Analog Neuron Devices for Hardware-based Spiking Neural Networks

To process data operations more efficiently in deep neural networks (DNNs), studies on spiking neural networks (SNNs) have been conducted. In the reported literature, CMOS neuron circuits that mimic the biological behavior of an integrate-and-fire function of neurons have been mainly studied. Because conventional neuronal circuits need to be improved in terms of area and energy consumption, neuron devices with memory functions such as resistive random access memory (RRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), floating body FETs, and ferroelectric FETs have been emerged to replace a membrane capacitor and trigger device in the conventional neuron circuits. In this review article, neuron devices that can increase the integration density of conventional neuronal circuits and reduce power consumption are reviewed. These devices are expected to play an important role in future neuromorphic systems.