Feedback Shift Register Research Articles

Hybrid FCSR Based Stream Cipher for Secure Communications in IoT

<p>Linear Feedback Shift Register (LFSR) is the basic hardware of stream cipher, and Feedback with Carry Shift Register (FCSR) is the nonlinear analogues of LFSR. FCSR is a feedback architecture to generate long pseudorandom sequence. In this paper, we study the characteristics of FCSRs combined with nonlinear circuits such as Dawson’s Summation Generator (DSG), lp-Geffe generator and etc. Then we proposed a hybrid FCSR applying DSG and lp-Geffe generator as nonlinear combining elements to increase the period and the linear complexity of the output sequence. In addition, we further investigate the period, linear complexity, randomness, and use known attacks to verify the security strength of the proposed keystream generator. The pass rates of the proposed scheme are 100% for FIPS PUB 140-1 random tests, and at least 98% for SP800-22 random test, respectively.</p> <p> </p>

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

A compressed sensing-based progressive secret image sharing scheme and security analysis

Cryptographic secret image sharing (SIS) allows a secret image to be shared among participants, and any authorized set of participants can reconstruct the secret. In this paper, we first propose a conceptually simple way to construct a progressive SIS scheme based on semi-tensor product compressed sensing (STP-CS). In the sharing phase, the dealer employs STP-CS to compress the secret image and extracts several different rows of the compressed image in turn. Then the sub-shadows for participants are formed. In addition, he needs to employ a perfect secret sharing to share the measurement matrix (or an initial state of the linear feedback shift register) among all participants. Finally, the sub-shadow and the share of the measurement matrix together constitute the shadow of each participant. In the combination phase, any legitimate access structure can reconstruct the secret image gradually. The perfect secret sharing ensures that the combination phase can work if and only if the access structure is authorized. Simultaneously, the use of STP-CS ensures that the proposed scheme has the properties of gradual reconstruction, noise-resilience, and smaller shadow size. Also, we have proven that the proposed scheme achieves the extended Wyner-sense perfect secrecy. Besides, we provide an extend version, referred to as homomorphic secret image sharing (HSIS), for improving the efficiency of the combination algorithm. HSIS can outsource the combination phase to the cloud servers securely.

Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification

The Tsetlin Machine (TM) is a machine learning algorithm based on an ensemble of Tsetlin Automata (TAs) that learns propositional logic expressions from Boolean input features. In this paper, the design and implementation of a Field Programmable Gate Array (FPGA) accelerator based on the Convolutional Tsetlin Machine (CTM) is presented. The accelerator performs classification of two pattern classes in 4 × 4 Boolean images with a 2 × 2 convolution window. Specifically, there are two separate TMs, one per class. Each TM comprises 40 propositional logic formulas, denoted as clauses, which are conjunctions of literals. Include/exclude actions from the TAs determine which literals are included in each clause. The accelerator supports full training, including random patch selection during convolution based on parallel reservoir sampling across all clauses. The design is implemented on a Xilinx Zynq XC7Z020 FPGA platform. With an operating clock speed of 40 MHz, the accelerator achieves a classification rate of 4.4 million images per second with an energy per classification of 0.6 μJ. The mean test accuracy is 99.9% when trained on the 2-dimensional Noisy XOR dataset with 40% noise in the training labels. To achieve this performance, which is on par with the original software implementation, Linear Feedback Shift Register (LFSR) random number generators of minimum 16 bits are required. The solution demonstrates the core principles of a CTM and can be scaled to operate on multi-class systems for larger images.

MTJ-based random number generation and its application in SNN handwritten digits recognition

Spiking Neural Networks (SNNs) that require synapse weight initialization using random numbers have been widely used in the neural morphological system. However, the random numbers generated by traditional digital circuits have certain repeatability, and the entire computing architecture has issues such as high resource consumption and low integration. In this letter, a hardware system for true random number generation is realized through integrating a magnetic tunnel junction, a memory cell of MRAM (magnetic random access memory) chips, with an interface circuit and using the same mechanism as writing data in spin transfer torque MRAM. The generated true random numbers are evaluated using NIST SP800-22 standard and are used for synapse weight initialization in an SNN system. The recognition rate of the system initialized by the generated true random numbers is about 84% for an MNIST handwritten digit dataset, which is 2%–3% higher than that using a traditional linear feedback shift register. The reported work provides a new approach for better SNN performance.

Multi-Layer QCA Shift Registers and Wiring Structure for LFSR in Stream Cipher with Low Energy Dissipation in Quantum Nanotechnology

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in designing the entire LFSR structure are design cost and energy efficiency, which are highly dependent on the SR structure. In the proposed study, the structural characteristics and problems of existing various types of SRs are presented, and new multi-layered serial-in-serial-out (SISO) and parallel-in-parallel-out (PIPO) SRs are proposed. In addition, we compare and analyze the area-time complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E. As a result, the proposed SISO and PIPO showed a performance improvement of more than 27% compared to the existing structure, which showed the best performance, and showed energy dissipation reduction rates of about 65% and 59%, respectively. In particular, we proposed multi-layer wiring that can reduce energy dissipation and verified through simulation that it can save up to 24.8%.

A Lightweight True Random Number Generator for Root of Trust Applications

There are many schemes proposed to protect integrated circuits (ICs) against an unauthorized access and usage, or at least to mitigate security risks. They lay foundations for hardware roots of trust whose crucial security primitives are generators of truly random numbers. In particular, such generators are used to yield one-time challenges (nonces) supporting the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise several concerns regarding the complexity of these solutions, both in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, all-digital lightweight and self-testable random number generator to produce a nonce. It builds on a generic ring generator architecture, i.e., an area and time optimized version of a linear feedback shift register, driven by a multiple-output ring oscillator. A comprehensive evaluation, based on three statistical test suits from NIST and BSI, show feasibility and efficiency of the proposed scheme and are reported herein.

Linear Feedback Shift Registers-Based Randomization for Image Steganography

Steganography involves concealing information by embedding data within cover media and it can be categorized into two main domains: spatial and frequency. This paper presents two distinct methods. The first is operating in the spatial domain which utilizes the least significant bits (LSBs) to conceal a secret message. The second method is the functioning in the frequency domain which hides the secret message within the LSBs of the middle-frequency band of the discrete cosine transform (DCT) coefficients. These methods enhance obfuscation by utilizing two layers of randomness: random pixel embedding and random bit embedding within each pixel. Unlike other available methods that embed data in sequential order with a fixed amount. These methods embed the data in a random location with a random amount, further enhancing the level of obfuscation. A pseudo-random binary key that is generated through a nonlinear combination of eight Linear Feedback Shift Registers (LFSRs) controls this randomness. The experimentation involves various 512x512 cover images. The first method achieves an average PSNR of 43.5292 with a payload capacity of up to 16% of the cover image. In contrast, the second method yields an average PSNR of 38.4092 with a payload capacity of up to 8%. The performance analysis demonstrates that the LSB-based method can conceal more data with less visibility, however, it is vulnerable to simple image manipulation. On the other hand, the DCT-based method offers lower capacity with increased visibility, but it is more robust.

A secure scan architecture using parallel latch-based lock

In this paper, we propose a new logic locking scheme to overcome scan-based side-channel attacks. The scheme is implemented using parallel latches and a key that includes a clock signal, which generates a different key for each design. With just a few parallel latches, the security of the scan design can be effectively improved. Meanwhile, we use a linear feedback shift register for dynamic obfuscation of the output. After the first call to the parallel latches, the response of the parallel latches is stored in ROM as the golden key. Our proposed secure scan design based on the parallel latch structure, which is unlocked using a key sequence and a test clock sequence, can protect encrypted chips from all known scan-based side-channel attacks. Additionally, our proposed scan design with the highest security only incurs an overhead of 0.225%, which outperforms most of the previously proposed secure scan designs. Experimental analysis shows that our design has high security and does not affect the testability of the chip.

Encryption Using Binary Key Sequences in Chaotic Cryptosystem

Transmission of images on the network is considered insecure which has security-related issues. In this paper, to provide security to digital images, an encryption system that uses four chaotic maps for binary key sequence generation is proposed. The system consists of stages namely, confusion, generation of random binary chaotic key sequence, pseudo-random number generation (RN), and diffusion. Keys for encryption are chosen randomly based on a pseudo random generator from the selected chaotic maps by the linear feedback shift register (LFSR). The algorithm achieves good results in terms of NPCR, UACI, and entropy values. The developed cryptosystem resists differential attacks, is sensitive to minor alterations in the keys, and has a large key space.

Encryption Using Optical Pseudo-Random Binary Sequence Based on Optical Logic Gate

In this paper, we propose a scheme for high-speed all-optical Pseudo-Random Binary Sequence (PRBS) generator and use it for generating keystream for encryption. This PRBS generator design is based on Linear Feedback Shift Registers (LFSR) and optical XOR and AND gates. The optical logical gates are based on quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI). With two photon absorption (TPA) in quantum dot-semiconductor optical amplifier (QD-SOA), this kind of optical logic gates performs well when processing data in an ultra-fast timescale and therefore able to function as high speed PRBS generator. Result shows that it’s possible for this scheme to realize all-optical encryption and decryption at high process rate up to 320 Gb/s. We simulated different ways of generating keystream with schemes such as cascaded generator, parallel generator and alternating step generator. These generators use more than one LFSR. Result shows that the schemes we use can function as stable and complex keystream generators.

A novel method for driven stability of NFSRs via STP

The nonlinear feedback shift register (NFSR) is the main component of the convolutional decoder. This paper provides a novel method for investigating the driven stability of NFSRs with input via semi-tensor product (STP). By using the STP method, a backward state transition matrix, as well as a backward NFSR, is constructed. Backward NFSRs can help to find the predecessors of any states so that an algorithm for the global stability of autonomous NFSRs is designed. On this basis, two algorithms are proposed for the driven stability of NFSRs with input, and they have lower computational complexity than the existing methods. Meanwhile, some numerical examples are presented to support the results of this paper. Finally, the relationship between stability and connectedness is discussed fully, which derives some interesting results.

ASIC vs FPGA based Implementations of Built-In Self-Test

Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.

Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.

Reconfigurable linear feedback shift register for wireless communication and coding

<p>Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.</p>

A novel reduced instruction set computer-communication processor design using field programmable gate array

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.

Modeling and physical attack resistant authentication protocol with double PUFs

As new lightweight hardware security primitive, the physical unclonable function (PUF) is used in various hardware-based secure applications like keys generation and device authentication. But PUFs are vulnerable to modeling attacks using machine learning (ML) technology. To solve the problem, a dynamically configurable obfuscation unit for PUF using a dynamic linear feedback shift register (DLFSR) is proposed. The structure of this obfuscation unit can change with the clock cycle running, making the PUF difficult to model. Using the obfuscation unit, a dual-PUF-based mutual device authentication protocol for low-cost IoT systems is proposed. New technologies like dual-stage and device-to-server authentication are used to limit the amount of data that an attacker can obtain. A random pattern-based mechanism is introduced to the protocol to enhance the robustness against physical attacks. A mathematical model of the proposed unit is presented and analyzed. Experimental results on FPGA show that the design is simpler, more reliable, and lightweight. It can effectively resist ML-based attacks and physical attacks.

A Lightweight authentication approach based on linear feedback shift register and majority function for internet of things

A Lightweight authentication approach based on linear feedback shift register and majority function for internet of things

Reduced complexity XOR trees for LDPC codes and BS-LFSR techniques to High-Speed memory applications

Low-Density Parity Check (LDPC) Codes exhibit dominant role which deal with limitation of storage capacity. Hardware realization of Parity Check Codes is slow and consumes more power which makes it vulnerable for the light weight applications. Hence, to improve the throughput, area and power dissipation, parity check architectures must be constrained. This article proposes architecture of LDPC codes for high-speed memory applications with comparable XOR-gate tree-based VLSI design. The designed extension module includes Bit Swapping Linear Feedback Shift Register (BS-LFSR) technique that can illustrate and gauge expansion of faults in both the versions of faulty and fault-free. Furthermore, the power dissipation has been reduced by 8% and area by 83% with its extension module. This work has been designed using Vivado HLS and the hardware implementation of BS-LFSR has been verified on Zync 7000 series FPGA board for faulty and fault-free test patterns.

Image encryption based on combined between linear feedback shift registers and 3D chaotic maps

Protecting information sent through insecure internet channels is a significant challenge facing researchers. In this paper, we present a novel method for image data encryption that combines chaotic maps with linear feedback shift registers in two stages. In the first stage, the image is divided into two parts. Then, the locations of the pixels of each part are redistributed through the random numbers key, which is generated using linear feedback shift registers. The second stage includes segmenting the image into the three primary colors red, green, and blue (RGB); then, the data for each color is encrypted through one of three keys that are generated using three-dimensional chaotic maps. Many statistical tests (entropy, peak signal-noise ratio (PSNR), mean square error (MSE) and correlation) were conducted on a group of images to determine the strength and efficiency of the proposed method, and the result proves that the proposed method provided a good level of safety. The obtained results were compared with those of other methods, and the result of comparing confirms the superiority of the proposed method.