A secure scan architecture using parallel latch-based lock

Abstract

In this paper, we propose a new logic locking scheme to overcome scan-based side-channel attacks. The scheme is implemented using parallel latches and a key that includes a clock signal, which generates a different key for each design. With just a few parallel latches, the security of the scan design can be effectively improved. Meanwhile, we use a linear feedback shift register for dynamic obfuscation of the output. After the first call to the parallel latches, the response of the parallel latches is stored in ROM as the golden key. Our proposed secure scan design based on the parallel latch structure, which is unlocked using a key sequence and a test clock sequence, can protect encrypted chips from all known scan-based side-channel attacks. Additionally, our proposed scan design with the highest security only incurs an overhead of 0.225%, which outperforms most of the previously proposed secure scan designs. Experimental analysis shows that our design has high security and does not affect the testability of the chip.