Capacitive Feedback Research Articles

Control Strategy for Disc Coreless Permanent Magnet Synchronous Motor with LC Filter

The disc coreless permanent magnet synchronous motor has the advantages of a short axial size, high power density, and small volume. Due to the coreless structure, its inductance is very small, which results in a serious current ripple and an unacceptable torque ripple if driven from a conventional inverter. This can be solved by installing an LC filter between the inverter and the motor. However, an undesirable resonance phenomenon is induced by the LC filter. In this paper, a new capacitive current feedback active damping (CCFAD) strategy is proposed. Instead of current sensors in the capacitor branch, a state observer is introduced to estimate the capacitance current. The observer is designed with double sliding mode surfaces, which reduces the order of the system. Compared to conventional capacitive current feedback, no additional current sensors are required, reducing the system cost. Besides the resonant harmonics, the phase current contains obvious fifth and seventh harmonics due to the special plane structure of the rotor. The proportional-integral-resonance (PIR) controller, instead of the traditional PI controller, is designed to suppress lower order harmonics. The experiment results show that current ripples due to resonance and rotor structure are suppressed significantly.

A theoretical investigation on wavefronts evolution governed by the modified Nagumo equation

A myelinated nerve fiber model with nonlinear membrane capacitance is considered, and the dynamics of the system is shown to be governed by the modified discrete Nagumo equation. Within the discrete limit, we examined saltatory conduction with the possibility of the capacitive feedback parameter influencing propagation failure. The time series solutions and profile of stationary impulses are equally investigated within the continuum limit approximation. This enhances our understanding of wavefronts initiation in the myelinated fiber under uniform and non-uniform excitabilities. We employed the Bilinear Hirota method and obtained wavefront solutions of the modified Nagumo equation. It is observed that an increase in the capacitive feedback parameter favors the narrowing of wavefronts, while its speed is rapidly increased; thereby enhancing excitability and transfer of neuronal information in the whole of the myelinated axon. The influence of capacitive feedback parameter on the stability of the homogeneous states, is equally brought into sharp focus. Results of numerical simulations of the modified discrete Nagumo equation, portrays a clear concordance with the analytical predictions. This is because the speed of the propagating anti-kink increases as the capacitive feedback parameter is gradually stepped up. We hope that future experimental investigations will validate the theoretical predictions highlighted in this study.

Comprehensive review and study for the CMOS transformer tank voltage‐controlled oscillator

AbstractThis article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (Q) and resonator coupling factor (κ). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance.

Research on the Control and Modulation Scheme for a Novel Five-Switch Current Source Inverter

Different from the voltage source inverter (VSI), the current source inverter (CSI) can boost the voltage and eliminate the additional passive filter and dead time. However, the DC-side inductor current is not a real current source and is generated by a DC voltage supply and an inductor. Under different switching states, the DC-side inductor will be charged or discharged, which leads to the DC-side inductor current being discontinuous or increasing. To solve the control problem of the DC-side inductor current of the CSI, a novel single-phase CSI topology with five switching tubes for grid-connected applications is proposed. Firstly, the reference calculation method and the hysteresis loop control scheme for the DC-side inductor current are proposed, and the adjustable and constant DC-side inductor current are obtained. Since the PWM signals cannot be directly implemented to the switching tubes, the modulation strategy for the single-phase CSI is proposed in this paper. Then, an active damping method based on the feedback capacitor voltage is presented to suppress the resonance peak caused by the LC filter on the grid side. Finally, the math model of the AC-side structure is established, and the optimal proportional-resonant controller parameters’ design method is explored by the amplitude–frequency characteristic curves. The simulation and experiment are implemented for the proposed CSI topology. The results show that a high-quality power with a good control performance can be obtained with the proposed CSI topology.

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

A Low-Power High-Sensitivity Photocurrent Sensory Circuit with Capacitive Feedback Transimpedance for Photoplethysmography Sensing.

This study presents an integrated analog front-end (AFE) tailored for photoplethysmography (PPG) sensing. The AFE module introduces a novel transimpedance amplifier (TIA) that incorporates capacitive feedback techniques alongside common drain feedback (CDF) TIA. The unique TIA topology achieves both high gain and high sensitivity while maintaining low power consumption. The resultant PPG sensor module demonstrates impressive specifications, including an input noise current of 4.81 pA/sqrt Hz, a transimpedance gain of 18.43 MΩ, and a power consumption of 68 µW. Furthermore, the sensory system integrates an LED driver featuring automatic light control (ALC), which dynamically adjusts the LED power based on the strength of the received signal. Employing 0.35 µm CMOS technology, the AFE implementation occupies a compact footprint of 1.98 mm × 2.475 mm.

Analysis and design of a 0.9 V 1 GHz-BW 14.6 dBm-OIP3 broadband receiver with current-mode analog baseband in 12 nm FinFET CMOS

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm2.

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Utilizing signal flow graph on multiple feedback amplifiers of NMC and DACFC with emphasis on design space exploration and conversion

SummaryOver a long time, different methods of frequency compensation of multistage amplifiers have been exploited for improvement in the behavior of stabilizing. In the present paper, the step‐by‐step conversion process of the dual active capacitive feedback compensation (DACFC) three‐stage amplifier into the nested Miller compensation (NMC) three‐stage amplifier is presented by a systematic approach and signal flow graphs (SFGs) based on the graph theory rules in graph domain. Also, according to graph rules, the conversion of the multiple feedback amplifier NMC into the multiple feedback amplifier DACFC is investigated in detail in the graph domain. During the conversion process, the difference in the gain‐bandwidth product (GBW) in the two mentioned case study's amplifiers is examined in terms of the graph at the system level. The elimination of two branches in one step of the conversion process of the SFG of the NMC into the SFG of the DACFC leads to a significant improvement in the behavior of GBW. This paper also conducts verification of the design of conventional NMC and DACFC amplifier circuits in HSPICE using 0.35‐μm CMOS technology and compares the circuit simulation results to SFG simulation results. In order to show the correctness of the idea, they are redesigned in HSPICE using 0.18‐μm CMOS technology, and appropriate results are obtained.

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB.

Nonsteady-State Electric Circuit in Electrophoresis on Paper: Thermal Consideration of Electrophoretic Lateral-Flow Assays.

Nonsteady-state behaviors are not expected in electric circuits that lack significant capacitance, inductivity, and/or active feedback. Here, we report that electrophoresis on paper─used, e.g., to electrophoretically driven lateral-flow immunoassays (LFIA)─can create a nonsteady-state electric circuit. We studied electrophoresis on 50 × 4 mm nitrocellulose membrane strips utilized in LFIA. The voltage was applied to strip termini immersed in reservoirs with a running buffer. If the electric power of this circuit exceeded approximately 0.5 W, neither the electric current nor the temperature map reached their steady states on a multiminute time scale. The current grew slowly to its maximum and then slowly decreased. The temperature map evolved slowly, with one or more hot spots appearing and disappearing gradually in different positions on the strip. The slow evolution of a temperature map led to the occurrence of a terminal hot spot in which the strip burned. No chaotic behavior was observed, i.e., time dependences of both the current and temperature map were reproducible. We analyzed major processes involved in paper-based electrophoresis and explained the nonsteady-state behavior. Unlike ordinary electric circuits with metal conductors, paper-based electrophoresis involves two slow processes: (i) intense buffer evaporation from hot spots and (ii) buffer supply from the reservoirs by an interplay of the capillary penetration and the electroosmotic flow. These processes affect heat generation and/or dissipation on the strip and, accordingly, the resistivity profile. The slow evolution of the resistivity profile is responsible for the nonsteady-state behavior. The results of our computer modeling support this explanation. The hot spots may have a destructive effect on electrophoretically driven LFIA. To avoid denaturation of immunoreagents, experimentalists should empirically confirm that spatiotemporal temperature maps are compatible with the developed assay.

Design of Photoelectric Positioning System and Realization of Its Positioning Mathematical Equation

The research of photoelectric positioning system based on wireless data transmission is a multidisciplinary research direction. In the design of photoelectric positioning system, the LED used for light sensing is selected as the light source, and the AC/DC isolated LED driving circuit based on AP3706 is designed. When designing photoelectric conversion circuit, considering the influence of noise interference on detection accuracy, a capacitor is added and connected in parallel with the feedback capacitor. In order to improve the detection accuracy, reduce the relative error of the four-channel signal processing process and maintain the consistency of the four channels, a noninverting amplifier circuit composed of four operational amplifiers LM324 amplifier chips is adopted in this study. NewMsg-RF2401 module is used for wireless data transmission. The system control module adopts ADμC841 single chip microcomputer as the control core. According to the characteristics of this single chip microcomputer, the corresponding ADC module input drive circuit and control-data transmission interface circuit are designed. While designing the hardware of the system, it is necessary to calculate the positioning position. In this study, a positioning mathematical equation is proposed, which can obtain the position of the moving target in the geographical area under the wireless transmission network. In the experiment, firstly, the implementation process of the positioning mathematical equation is described, and then the performance of the proposed positioning mathematical equation is compared with that of the random positioning equation and the binary positioning equation. The results show that more messages can be transmitted by using the positioning mathematical equation proposed in this study. Based on this, it is used in the positioning system designed in this study, which is unfolded under the condition of constant background light, adjusts the position of the movable light source and determines the position coordinates. According to the horizontal and vertical displacement of the light source detected by the system, the positioning error is less than 0.1%, which is in line with the design expectation.

An analytical approach to designing millimeter‐wave LNAs with transformer‐based matching networks

AbstractIn this article, an analytical method for designing transformer matching network of millimeter‐wave (mm‐wave) low noise amplifier (LNA) is presented. In the circuit design, neutralizing capacitors (NCs) structure is used to mitigate the intrinsic gate‐drain feedback capacitance in the transistor for increasing the reverse isolation and available gain, thus allowing the common source (CS) structure can be regarded as an unilateralized active amplification part. The equivalent circuit of the active amplification part and the matching transformer network is modeled, then the analytical matching equations can be established, and the required matching transformer parameter can be determined quickly. As a proof of concept, a Ka‐band LNA operating at 37–43 GHz is designed and implemented in 65 nm complementary metal oxide semiconductor. The measured results show that the small signal gain of the circuit is 19.2–20.5 dB at 37–43 GHz. The noise figure (NF) in the operating band is 3.2–4.2 dB, and the minimum NF is 3.2 dB at 40.2 GHz. The chip area is only 0.08 mm2 excluding pads.

A Sensory Soft Robotic Gripper Capable of Learning-Based Object Recognition and Force-Controlled Grasping

Soft robotic grippers possess high structural compliance and adaptability, allowing them to grasp objects with unknown and irregular shapes and sizes. To enable more dexterous manipulation, soft sensors that are similar in mechanical properties to common elastomer materials are desired to be integrated into soft grippers. In this paper, we develop ionic hydrogel-based strain and tactile sensors and integrate these sensors into a three-finger soft gripper for learning-based object recognition and force-controlled grasping. Such hydrogel-based sensors have excellent conductivity, high stretchability and toughness, good ambient stability, and unique antifreezing property; they can be readily attached to a soft gripper at desired locations for strain and tactile sensing. By using a deep-learning model, the sensory soft gripper is demonstrated to be capable of grasping and recognizing objects at both room and freezing temperatures, and achieving close to 100% recognition accuracy for ten typical objects. Moreover, the capacitive tactile feedback of the gripper is utilized to develop a closed-loop force controller and realize force-controlled grasping of fragile or highly deformable objects. A new slip detection and compensation strategy is also proposed and validated for the sensory gripper for adjusting the grasping force in real time upon detecting slippage. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —The multimodal sensation of a soft robotic gripper could enrich its grasping functionalities and improve its manipulation performance. This research integrates novel antifreezing ionic hydrogel-based strain and tactile sensors into a three-finger soft robotic gripper for learning-based object recognition and force-controlled grasping. Constructed from a highly stretchable, ambient-stable, and antifreezing ionic hydrogel, the strain and tactile sensors can be readily integrated at the desired locations on the soft gripper, and can reliably operate at both ambient and freezing temperatures with excellent mechanical and electrical properties. Based on the feedback of the strain and tactile sensors, a deep learning model is employed to enable high-accuracy object recognition while grasping, which can be useful for manipulation in vision-free environments. Closed-loop force control and slip compensation strategies are also demonstrated for reliably grasping fragile/deformable objects and handling slip events during the manipulation of heavy objects. The sensory soft gripper and the associated object recognition and force control methods could find practical applications in a variety of robotic manipulation tasks.

Pseudo-Resistor-Based ECG Amplifier: Design, Implementation and Temperature Characterization

Biomedical signal amplifiers are fundamental in various medical applications for acquiring crucial biological signals such as ECG, EEG, and EMG. The use of pseudo-resistors has been recently studied for biological amplifiers, mainly because of their fast recovery time after interference pulses, which are frequent in such applications. The previous studies on pseudo-resistors are limited to simulation, modeling, and implementing some narrow-bandwidth amplifiers. For the first time, this study uses the piecewise linear (PWL) model integrated with pseudo-resistors to design a tailored circuit for ECG applications, with 0.04 Hz to 2 kHz bandwidth for the full application temperature range. The circuit is fully modeled, simulated, and characterized, fine-tuning the feedback capacitance values to optimize performance within the crucial temperature range for biomedical applications. This full bandwidth amplifier represents a significant advancement in biomedical signal amplification technology, ensuring comprehensive signal fidelity allied to fast recovery response.

A Low-Distortion Low-Power MASH Architecture ΣΔ Modulator with Double-Sampling

This paper presents a low-distortion and low-power multi-stage noise-shaping (MASH) architecture Sigma-Delta ([Formula: see text] modulator with double-sampling. The modulator uses a cascade of integrator feed-forward (CIFF) structure as a cascaded modulator in a MASH architecture. Since the CIFF structure provides a feedforward path from the input signal to the quantizer, the input signal is directly transmitted to the output without loop processing, relaxing the linearity requirement of the modulator, reducing performance requirements for the OTA and harmonic distortion. Double-sampling technique is adopted in the first integrator to double the sampling rate, improving the accuracy of the modulator without the increase of power consumption. In order to eliminate the influence of capacitor mismatch in the sampling network, a fully floating differential switched capacitor (SC) feedback digital-to-analog (DAC) is used in the integrator. The simulation results show that the [Formula: see text] modulator achieves 113[Formula: see text]dB signal-to-noise and distortion ratio (SNDR) and the power consumption is 3.15[Formula: see text]mW from a 5[Formula: see text]V power supply.

A 0.45‐V low‐power low‐noise amplifier using a wideband image‐rejection technology

AbstractA 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power.

Low power and low phase noise complementary voltage controlled oscillator optimised by a meta‐heuristic algorithm

AbstractThis paper presents a differential complementary metal oxide semiconductor inductor‐capacitor voltage controlled oscillator (LC‐VCO). The VCO is adopted from the gate‐to‐source capacitor feedback Colpitts VCO which has the advantage of large value of negative conductance. Due to the large negative conductance, the VCO has a more reliable startup oscillation at the lower currents. The main characteristics of the VCO such as negative conductance, oscillation frequency and phase noise are discussed and analysed. The value of parameters in this circuit have been determined using Non‐dominated Sorting Genetic Algorithm (NSGA‐II) to have the optimum performance. The designed VCO oscillates at 2.76 GHz under a supply voltage of 1.4 V. Power dissipation of the proposed VCO is 873 μW which is significantly lower than that of some other VCOs. The post‐layout simulation results of the proposed VCO are presented and compared with the performance of some other VCOs.

A 4.5 μW Miniaturized 3-Channel Wireless Intra-Cardiac Acquisition System.

This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 μVrms, and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 μm standard CMOS technology and consumes 4.5 μW while occupying 1.125 mm2.

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.

This article presents a low-noise high-power-efficiency analog front-end (AFE) for capacitive-micromachined-ultrasonic transducers (CMUT). Implemented in 28-nm CMOS technology, the proposed AFE features three-stage continuous time-gain compensation (TGC) embedded in both trans-impedance amplifiers (TIAs) and an analog beamformer to provide a large compensation range with no extra power-consumption cost. The use of noise cancellation and capacitive feedback optimizes the noise performance of TIAs. The first stage of the TGC is built in the TIA by adjusting the positive and negative resistance loads, which are composed of voltage-controlled transistor arrays. An all-pass passive network is used as the delay unit of the analog beamformer, meanwhile achieving the second TGC stage. Phase shift for all frequency components in the ultrasound pass-band is manifested as a delay to the echoes. The third stage of the TGC is merged with a summing unit, which is a closed-loop amplifier with variable resistance feedback. The design takes into account the ability to handle large signals and power consumption, with TIA and beamforming operating at voltages of 2.5 V and 0.9 V, respectively. Experimental results show that the proposed AFE achieves a 2.11 pA/√Hz input-referred noise (IRN) at the 5 MHz center frequency of the echoes while consuming only 1.02 mW/channel. A total exponential TGC range of 60 dB with continuous ranges of 12 dB, 24 dB, and 24 dB assigned to three stages has been verified for this work.