Capacitive Feedback Research Articles

AWAGS: A single ASIC to identify fast ions from protons to uranium

New tracking detectors are necessary for beam diagnostics and event-by-event particle identification for the Super-FRS, a next generation reaction product separation being constructed at GSI/FAIR in Germany. Novel detectors and electronics are currently being developed to meet the stringent requirements of this forefront fragment separator due to high radiation levels, long term electronic stability and the required homogeneity of materials in the beam, while maintaining very high tracking efficiency. The present contribution focuses on the electronics for a new Gas Electron Multiplier (GEM)-based Time Projection Chamber (TPC) to provide the position information, which are needed to reconstruct the A/q of the fragment from protons to uranium ions. The most recent Front End Electronics (FEE) developed at GSI with a novel Amplifier With Adaptive Gain Settings (AWAGS) ASIC are being tested. This FEE has a low noise level (sub fC), a large dynamic range (up to ∼71pC) with excellent timing properties. The AWAGS uses a switched capacitance technique instead of fixed feedback capacitors to provide the large dynamic range. Results from the ASIC characterisation studies and the outlook for a new, updated chip for the full read out chain of the GEM TPC are presented.

Fin Field-Effect Transistor (FinFET) Based Low Noise Low Power Chopper Stabilized Capacitively Coupled Amplifier for Biosignal Acquisition System

Design of low power and low noise amplifier for biomedical signal acquisition is quite challenging. In this paper, an inverter based chopper stabilized capacitively coupled amplifier is designed for biomedical applications using 14 nm FinFET technology. Single-stage inverter based amplifier which is used as a core amplifier in the proposed chopper stabilized circuit is designed and compared using different configurations of FinFET and CMOS. Gain and power dissipation is better with fully FinFET based single-stage amplifier when compared with fully CMOS based counterpart. When the FinFET based amplifier is used with capacitive feedback and chopper stabilization circuit, it provides a significant reduction of noise as shown by Noise Efficiency Factor (NEF) of 3.66. The gain in chopper stabilized amplifier is 36.7 dB and bandwidth is in the range of 9.16 Hz–7.6 kHz. The CMRR and PSRR of the designed amplifier are 96.1 dB and 98.5 dB respectively. The power dissipation of the amplifier is 1.24 μW which is relatively better. In the end, spike reduction circuitry is also used successfully to minimize the spikes in the output signal.

Low noise amplifier with adaptive gain setting — (AWAGS) ASIC

The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture is followed by a single-ended to differential conversion and output buffers. To the contrary to usual ASIC designs, the capacitive feedback is divided into five capacitances with different values. Starting with the smallest one the capacitances are added to the feedback depending on the input charge. This concept allows to measure over a high dynamic range (>200000) with the highest precision in the individual gain setting. The AWAGS ASIC is produced in a UMC 180 nm UMC multi-project wafer (MPW) run 2020.

Localized nonlinear waves in a myelinated nerve fiber with self-excitable membrane

We systematically study the evolution of modulated nerve impulses in a myelinated nerve fiber, where both the ionic current and membrane capacitance provide the necessary nonlinear feedbacks. This is achieved by using a perturbation technique, in which the Liénard form of the modified discrete Fitzhugh–Nagumo equation is reduced to the complex Ginzburg–Landau amplitude equation. Three distinct values of the capacitive feedback parameter are considered. At the critical value of the capacitive feedback parameter, it is shown that the dynamics of the system is governed by the dissipative nonlinear Schrödinger equation. Linear stability analysis of the system depicts the instability of plane waves, which is manifested as burst of modulated nerve impulses that fulfills the Benjamin–Feir criteria. Variations of the capacitive feedback parameter generally influences the plane wave stability and hence the type of wave profile identified in the neural network. Results of numerical simulations mainly confirm the propagation, collision, and annihilation of nerve impulses in the myelinated axon.

Negative Feedback Programmable Charge Amplifier for Control Piezoelectric Sensors

This paper describes the design and operation of a programmable charge amplifier for a piezoelectric sensor. An operational amplifier (op-amp) circuit operates the charge amplifier. The purpose of this paper was to design and explain a novel approach for programmable charge amplifiers. A programmable charge amplifier is created by a host digitally (Serial Peripheral Interface (SPI)) and a network of negative feedback, which is a network of resistors and capacitors (RC) connected between an output and inverter input node of an op-amp, where the feedback capacitor is 15 pF and resistors are 12.5, 25, 50, 100, and 200 k. The analog switch was used to connect serial to RC and subsequently to SPI. The suggested circuit was developed and evaluated using discrete components; also, the programmable circuit design and results were generated using Linear Technology's Integrated Circuit Emphasis (LTSPICE) simulation software. It is powered by a ±5V battery. The open loop (AOL), Noise Gain (NG), and phase margin have all been demonstrated in ac analysis. AOL and UGF are set for varied all switches (AOL 107.26 dB and UGF 8.6 MHz), however NG exhibits stability when the feedback capacitor is larger than 15 pF and the feedback resistance is fixed since the design has a Rate-Of-Closure (ROC) smaller than 20 dB. On the other side, the phase margin is also stable. When the switches (the 5-bits of SPI) are activated, the feedback capacitor is set to 15 pF, resulting in the optimum stability, output voltage, settling time, and slew rate. These have been completed in the time domain (transient analysis).

Design methodology of a 28 nm FD-SOI capacitive feedback RF LNA based on the ACM model and look-up tables

The race to reduce the size and improve power consumption in new transistor technologies has given rise to design trade-offs that are difficult to address with standard methodologies that require an iterative process. This paper proposes a design methodology based on the ACM model and look-up tables to quickly size a 28 nm FD-SOI RF LNA that is intended to work down to 233.15 K as demonstrated with post-layout simulation results. The design incorporates different tuning knobs that might be useful for allowing the circuit to work at cryogenic temperatures during experimental measurements, ultimately allowing the circuit to work down to 4 K for quantum device measurements.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications

AbstractA 28 GHz two stage low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. The envelope detection circuit turn‐on the second half of the LNA by the RF signal input received at the first stage. The default gain is increased (31.53%) by the tunable negative feedback capacitor circuit of the LNA with the control voltage from 0 to 1 V. In addition, 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB. The first stage of the LNA is designed with the inductive source degeneration for the noise reduction, and the multiple‐gate topology is involved in the second stage to improve the linearity. The third‐order input intercept point and the noise figure of the LNA are −7 dBm and 2.86 dB, respectively. When the second stage is turned‐on and turned‐off the LNA consumes 7.4 mW and 5.8 mW of power, respectively, from the 1 V supply. The proposed LNA requires 0.19 mm2 of core area. The performance of the LNA under process corner variation and temperature variation are analyzed.

AC coupled amplifier with a resistance multiplier technique for ultra-low frequency operation

This paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. This is accomplished by actively boosting the output resistive value of a MOS transistor in weak inversion. The circuit is based on a more general architecture, recently proposed by the authors, and is analyzed in terms of its capability to achieve ultra-low frequency operation, its DC performance, and noise. The proposed technique is demonstrated via measurement results from a fabricated test chip prototype using a standard 0.18 µm CMOS technology. The proposed amplifier provides a tunable high pass corner frequency from 20 mHz to 475 mHz, consuming 4.71 μW and a total area of 0.069 mm2.

Static DC Transformer Based on Negative Capacitance and High Voltage Engineering

Abstract: For DC voltage amplification, the operational amplifier is mostly used in the non-inverting configuration. In this case, the DC voltage amplification is done using a negative capacitance converter. Since the feedback capacitor acts as an open circuit for DC signal, it provides isolation between input and output. The amplified voltage level is limited by the breakdown voltage of the transistors used to build the op-amp and further the insulation breakdown limit of the Miller capacitor. By making use of new technologies such as silicon carbide technology, the breakdown voltage of transistors can be made higher even 1.2 KV and combined with high voltage engineering for capacitive insulation such as polymer capacitors, this can become a huge breakthrough in electric power engineering. Additionally, it can be used as a effective DC source for electric vehicles. The nominal voltage used in hybrid vehicles ranges from 100V to 200V.For electric-only vehicles, the required voltage is as high as 800V.The simulations are done using MIT Circuit sandbox, an open source circuit simulation tool. Keywords: DC amplifier, Op-amp, negative capacitance, silicon carbide and high voltage insulation.

Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT

Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and &gt;20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE &gt; 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and &gt;12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. POUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.

A Mixer-First Receiver With Class-F Adiabatic Switching

This letter introduces the use of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">class-</i> F adiabatic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">switching</i> in a mixer-first 2.45-GHz ISM-band receiver. By using the principle of adiabatic switching with a class-F VCO, a resonant multiharmonic drive for an N-path-based mixer-first receiver is generated, resulting in a reduced power consumption while maintaining a good mixer noise figure (NF). To optimize the area, coupled inductors in the VCO are used. By employing a switched capacitor (SC) feedback network in the baseband (BB) amplifier, a proper input matching and flexible common-mode (CM) bias is achieved. A packaged chip implemented in 28-nm CMOS achieves a low-power consumption of 3.5 mW with a gain of 22 dB and an NF of 7.4 dB.

A Low-Power Digital Capacitive MEMS Microphone Based on a Triple-Sampling Delta-Sigma ADC With Embedded Gain

A triple-sampling &#x0394;&#x03A3; ADC can replace the programmable gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18 &#x03BC;m CMOS process, had an area of 0.98 mm², achieved an A-weighted SNR of 62.1 dBA at 94 dBSPL with 520 &#x03BC;A current consumption, to which triple-sampling was shown to contribute 4.5 dBA.

Multi-channel analyzer based on a novel pulse fitting analysis method

A novel pulse fitting analysis (PFA) method is presented for the acquisition of nuclear spectra. The charging process of the feedback capacitor in the resistive feedback charge-sensitive preamplifier is equivalent to the impulsive pulse, and its impulse response function (IRF) can be obtained by non-linear fitting of the falling edge of the nuclear pulse. The integral of the IRF excluding the baseline represents the energy deposition of the particles in the detector. In addition, since the non-linear fitting process in PFA method is difficult to achieve in the conventional architecture of spectroscopy system, a new multi-channel analyzer (MCA) based on Zynq SoC is proposed, which transmits all the data of nuclear pulses from the programmable logic (PL) to the processing system (PS) by high-speed AXI-Stream in order to implement PFA method with precision. The linearity of new MCA has been tested. The spectrum of 137Cs was obtained using LaBr3(Ce) scintillator detector, and was compared with commercial MCA by ORTEC. The results of tests indicate that the MCA based on PFA method has the same performance as the commercial MCA based on pulse height analysis (PHA) method and excellent linearity for γ-rays with different energies, which infers that PFA method is an effective and promising method for the acquisition of spectra. Furthermore, it provides a new solution for nuclear pulse processing algorithms involving regression and iterative processes.

Improvement of sigma delta charge readout method for radiation detector application

Recently, a novel charge readout method has been developed based on 1-bit sigma delta modulation, which is able to directly achieve a Charge-to-Digital Conversion (QDC). This kind of design mainly comprises an amplifier and an FPGA instead of the conventional Front End Electronics (FEE) for radiation detectors. The amplifier is responsible for charge integration, and the FPGA is used for linear discharging. All of post-processing algorithms are implemented in the FPGA. Targeting this kind of readout method, some improvements are made to extend its application for new radiation detectors. In first improved version, a feedback resistor for baseline stabilization and a trigger threshold for removing noise signal are introduced. The feedback resistor leads to a slow exponential discharging when a charge signal is integrated on the feedback capacitor. To choose optimized parameters, an analysis of the exponential discharging effect on the linear discharging is made. In second version, an artful improvement is proposed to discard the exponential discharging. To evaluate the improved readout method, a 32-channel readout electronics prototype is developed. The performances and analysis of the circuit, such as channel linearity, dead time, are also presented. A SiPM based detector module is applied to verify this electronics prototype. The experimental results show that this new kind of charge readout is efficient and promising for other radiation detectors.

Grid-Connected Resonance Suppression Of Group-Series Photovoltaic Cluster Inverters Based On Hybrid Damping

Grid-connected group-series photovoltaic cluster inverter system will cause resonance, which will adversely affect the system. To suppress grid-connected resonance, the mathematical model, resonance mechanism and resonance characteristics of the cluster inverters are analyzed, and a global resonance suppression strategy based on hybrid damping is proposed. In the current loop of the inverter, capacitive current feedback and parallel voltage proportional feed-forward are introduced as active dampers to reduce the harmonics of the parallel current. On this basis, RLC type second-order resonance suppression circuit is added as passive damping to suppress system resonance, so that the output current of the inverters can meet the grid-connected conditions when the cluster is connected to the grid. The simulation and experimental results show that the total harmonic distortion of the grid-connected current decreases from 10.54% to 1.97% after three series photovoltaic cluster inverters adopt this strategy, which effectively suppresses the grid-connected resonance.

Ultra-low power signal conditioning system for effective biopotential signal recording

Design of Low-power signal conditioning system comprising of biopotential amplifier (BPA) and low pass Filter (LPF) remains one of the most critical block of system on chips (SoCs) targeted for wearable non-invasive and semi-invasive biomedical applications like electroencephalography and electrocorticography. Design of the same is a challenging task owing to noise-power trade-off in BPA and dependency of process voltage and temperature variations on the filter circuit. We report the design of a signal conditioning system comprising of a capacitively coupled capacitive feedback (CC-CF) BPA and composite p-channel metal oxide semiconductor (PMOS) based complementary source-follower LPF. The results obtained in Cadence with standard 0.18 µm technology and BSIM3V3 MOS models for the proposed signal conditioning system provide a DC-gain value of 36.76 dB, bandwidth of 280 mHz–174 Hz, power consumption of 24.54 µW, supply current of 24.54 µA, area consumption of 0.212826 mm2 from 0.5 V supply voltage. Robustness of this signal conditioning system has been checked by performing 200 runs of monte carlo simulations. The statistical results obtained for gain of (CC-CF) BPA, complementary source follower (CSF-C) LPF and signal conditioning system show mean (µ) values of 39.93 dB, −3.92 dB and 35.96 dB as well as standard deviation () of 135.433 mdB, 1.90 dB, and 2.00 dB respectively. The CC-CF BPA architecture, CSF-C LPF and complete signal conditioning system are expected to be used in SoCs targeted for various low-power biomedical applications.

Computer‐aideddesign methodology for inductive compensated microwaveclass‐Epower amplifier

This article presents a simulation-based analysis to first evaluate the impact of excessive transistor output capacitance on class-E power amplifiers and to second show how inductive compensation can be used to recover optimum class-E operating conditions. As a starting point, the finite-feed inductor in a parallel-circuit topology is replaced by a frequency-dependent inductor, which in turn can be substituted by a network composed of a series inductor and additional subharmonic resonators. This complex lumped-element network is then replaced by a generalized transmission line equivalent topology, suitable for microwaves. Calculation of the transmission line impedances and electrical lengths of the proposed generalized network is shown in detail and a design procedure for this modified class-E is provided. The analysis presented here is further extended by using a simplified large-signal model for the employed GaN HEMT device, which allows evaluating the effects of non-ideal switching as well as of capacitance voltage-dependency and feedback capacitance. The analysis is validated by simulation and design of a test board. Measurements of the test board showed a drain efficiency of 80.3%, power-added efficiency of 76.3% and output power of 40.1 dBm at 1.96 GHz, demonstrating the validity of the proposed approach.

Improved active damping control strategy and closed-loop parameter design for LCL grid-connected inverter

In this paper, an active damping control strategy based on capacitance and voltage feedback is proposed to solve the resonance problem of three-phase LCL inverter grid-connected system. To solve the problem that the parameters of active damping control strategy are complicated and need to be adjusted repeatedly, a parameter design method is proposed in this paper, which is simple to implement and does not need to be adjusted repeatedly. Finally, the effectiveness of the control strategy and parameter design method is verified by experiments.

An ultra-low noise pseudomorphic high electron mobility transistor (pHEMT)-based low noise amplifier using low temperature co-fire ceramic (LTCC) technique

PurposeThis study aims to present two stage pseudomorphic high electron mobility transistor-based low noise amplifier (LNA) designed using low temperature co-fire ceramic (LTCC) technique for ultra-high frequency (UHF) band. The LNA operates in the frequency range of (400∼500) MHz which is suitable for wireless communication applications.Design/methodology/approachThis LNA uses resistive capacitive (RC) feedback in the first stage to have wide bandwidth and interstage network for gain enhancement. By using external RC feedback, stability is improved and noise matching in the input stage is isolated by decoupling inductor. The excellent performance parameters including gain, noise figure (NF), wideband and linearity are attained without affecting the power consumption, compactness and cost of the proposed design.FindingsSimulation is carried out using advanced design software and the result shows that gain of 33.7 dB, NF 0.416 dB and 1 dB compression point (P1dB) of 18.59 dBm are achieved with a supply voltage of 2.5 V. The return loss of input and output are −19.3 dB and −10.5 dB, respectively. From the above aforementioned parameters, it is confirmed that the proposed LNA is a promising candidate for receivers where high gain and very low NF are always demandable with good linearity for applications operating in the UHF band.Originality/valueThe innovation of the proposed LNA is that the concurrent attainment of high gain, low NF, wideband, optimum input matching, good stability by RC feedback and interstage network using LTCC technique to achieve robustness, low cost and compactness to prove the applicability of design for wireless applications.