Detectable Faults Research Articles

Ball grid array (BGA) solder joint intermittency real-time detection

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

On Complete Functional Broadside Tests for Transition Faults

It was shown before that tests applied under nonfunctional operation conditions, which are made possible by scanning in an unreachable state, may lead to unnecessary yield loss. To address this issue, functional broadside tests were defined as broadside tests that use only reachable states of the circuit as scan-in states. Earlier procedures for generating functional broadside tests were not complete, i.e., they did not always detect all the detectable faults or prove that all the undetectable faults are undetectable. In this paper, we address the completeness of the functional broadside tests for transition faults. We describe the implementation of a test-generation procedure that can, for every transition fault, either find a functional broadside test or prove that the fault is undetectable under the functional broadside tests. We present experimental results where complete results are achieved for almost all the benchmark circuits considered.

Robust Fault Detection Linear Interval Observers Avoiding the Wrapping Effect

In model based fault detection is very important to analyze how the effect of model uncertainty is considered when determining the optimal threshold to be used in residual evaluation. In case of model uncertainty is located in parameters (interval model), an interval observer has been shown to be a suitable strategy to generate this adaptive threshold. However, interval observers can be affected by the wrapping effect when low computational algorithms, such as region-based approaches coming from the interval community, are used to determine the predicted output interval. This paper shows that the wrapping effect might be avoided forcing the observer gain to satisfy the isotonicity condition. Then, the effect of this observer condition on the time evolution of the residual sensitivity to a fault and the minimum detectable fault is analyzed in order to see whether the fault detection performance is enhanced or not. Finally, an example based on an industrial servo actuator will be used to illustrate the derived results.

$z$-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs

Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.

A Self-Reconfigurable Platform for Built-In Self-Test Applications

This paper introduces a novel architecture that is targeted for digital core testing and built-in-self test (BIST) algorithm development. This reconfigurable architecture is validated by an application that implements the novel idea of verifying algorithms for testing digital circuits by using runtime reconfigurable techniques in order to minimize the circuit area, as well as the test generation and application time. The idea revolves around the dynamic partial reconfiguration of circuits under test in order to inject stuck-at faults at different locations of the circuit and uncover both detectable and undetectable faults. Four testing strategies are presented, and two are experimentally compared, namely, the sequential compile-time reconfiguration and runtime reconfiguration strategies.

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture

Fault detection test set for testable realizations of logic functions with ESOP expressions

The circuit testable realization and its fault detection for logic functions with ESOP (EXOR-Sum-Of-Products) expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n + m + 1 vectors for the detections of AND bridging faults and a test set with 2n + m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using XOR gate tree, a test set with 2n + m vectors for the detections of AND bridging faults and a test set with 3n + m + 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n + 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.

PERFORMANCE EVALUATION OF KALMAN FILTER FOR FAULT DETECTION OF HYDRAULIC ACTUATORS

In this paper, an Extended Kalman-Bucy-Filter approach for fault detection and diagnosis of an hydraulic servo-axis is presented. The filter improves the results with the EKF as reported in literature since it uses a new model structure, considers nonlinear valve spool displacement-flow relationships and incorporates temperature effects. The performance of the newly proposed architecture is evaluated thoroughly at a testbed in the presence of both process faults and sensor faults. For sensor faults, the smallest reliably detectable sensor fault is determined. The method is finally compared to parity equations and parameter estimation, which have also successfully been applied to the supervision oif hydraulic servo axes.

Reliability Computation of Moranda's Geometric Software Reliability Model

The Jelinski-Moranda (JM) model for software failures was one of the first models used for analyzing software reliability. Later Moranda proposed a modification of the JM model, labeled Geometric de-Eutrophication model. In the Moranda Geometric de-Eutrophication model, N(t) is defined as the number of faults detected in the time interval (0,t]. In this paper, N(t) is assumed to be a pure stochastic birth process, where failure rates decrease geometrically with a detection and rectifying of a fault. In this paper, a recursive scheme is proposed for studying the probability of detecting n bugs in the time (0,t]. The method uses a constructed table, which makes the method easier compared to other existing methods for computing Pn(t), the intensity function and the reliability Rτ(t). In the proposed procedure Pn(t) is the sum of (n+1) terms and each term is based on a factor, which can be from the above mentioned table.

REDUCING THE SIZE OF DETECTABLE FAULTS IN NONLINEAR SYSTEMS

AbstractThe problem of threshold selection for fault detection in nonlinear systems is considered. For the linear case the existing result requires of factorization of transfer function from perturbations to the output. In the nonlinear case a different approach is proposed in this work. Using ideas based on the concept of uniform ultimate boundedness a procedure to construct a residual generation is considered. The residual obtained is defined in such a way that a corresponding threshold can be defined in a natural form, in fact, as term in the residual equation. The proposed threshold can reduce the size of detectable faults and in this way the result is comparable to the existing for linear systems. The benefits of the approach are discussed.

Residual Generation for Fault Diagnosis of Systems Described by Linear Differential-Algebraic Equations

Linear residual generation for differential-algebraic equation (DAE) systems is considered within a polynomial framework where a complete characterization and parameterization of all residual generators is presented. Further, a condition for fault detectability in DAE systems is given. Based on the characterization of all residual generators, a design strategy for residual generators for DAE systems is presented. The design strategy guarantees that the resulting residual generator is sensitive to all the detectable faults and also that the residual generator is of lowest possible order. In all results derived, no assumption about observability or controllability is needed. In particular, special care has been devoted to assure the lowest-order property also for non-controllable systems

An adaptive particle filter for mobile robot fault diagnosis

An adaptive particle filter for fault diagnosis of dead-reckoning system was presented, which applied a general framework to integrate rule-based domain knowledge into particle filter. Domain knowledge was exploited to constrain the state space to certain subset. The state space was adjusted by setting the transition matrix. Firstly, the monitored mobile robot and its kinematics models, measurement models and fault models were given. Then, 5 kinds of planar movement states of the robot were estimated with driving speeds of left and right side. After that, the possible (or detectable) fault modes were obtained to modify the transitional probability. There are two typical advantages of this method, i.e. particles will never be drawn from hopeless area of the state space, and the particle number is reduced.

A new method for the detections of multiple faults using binary decision diagrams

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram (BDD). First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

11.3.3 Enabling Measurement‐Driven System Development by Analyzing Testing Strategy Tradeoffs

ABSTRACTMeasurement‐driven system development focuses on using quantitative data to evaluate capabilities, benefits, progress, and tradeoffs as well as identify improvement opportunities. This paper describes a controlled study that addresses software testing effectiveness and focuses on the combination of individual testing techniques into team‐based testing strategies. This analysis is intended to enable measurement‐driven process improvement by characterizing how testing effectiveness relates to several factors, including testing strategy, software type, and developer expertise. In this study, a representative group of software development professionals applied common testing techniques to different types of software. This study compares the six possible team combinations of three testing techniques: (1) code reading by stepwise abstraction, (2) functional testing using equivalence partitioning and boundary value analysis, and (3) structural testing using 100% statement coverage criteria. Thirty‐two professional developers applied the techniques to three unit‐sized programs in a fractional factorial experimental design.The major results of this study are the following. The six combined testing strategies detected 17% more of the programs' faults on the average than did the three single techniques, which was a 35% improvement in fault detection. The highest percentages of the programs' faults were detected when there was a combination of either two code readers or a code reader and a functional tester. However, a pairing of two code readers detected more faults per hour than did a pairing of a code reader and a functional tester. The pairing of two individuals of advanced expertise resulted in the highest percentage of faults being detected. The most cost‐effective (number of faults detected per hour) testing strategy overall was when code reading was applied by an individual. The most cost‐effective combined testing strategy was when a code reader was paired with either another code reader or a structural tester. Both the percentage of faults detected and the fault detection cost‐effectiveness depended on the type of software being tested. In conclusion, we outline future research directions that build on these strategies and ideas.

On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan

Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transition probabilities, instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. It is demonstrated that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits. The case where the circuit has a single scan chain, and the case where the circuit has multiple scan chains are considered.

Optimisation of the stress distribution in ceramic hip joint balls by implementation of biological growth

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

AN ALGORITHM FOR DETECTING FAULTS IN RAILWAY POINT MECHANISMS

The main purpose of this paper is to implement a system capable of detecting faults in point mechanisms of railway infrastructure. This is achieved by developing an algorithm that takes advantage of three empirical criteria simultaneously capable of detecting faults from records of measurements of force against time. The system is dynamic in several respects: the base reference data is computed using all the curves free from faults as they are encountered in the experimental data; the algorithm that uses the three criteria simultaneously may be applied in on-line situations as each new data point becomes available; and recursive algorithms are applied to filter noise from the raw data in an automatic way. Encouraging results are found in practice when the system is applied to a number of experiments carried out by an industrial sponsor.

Discussion on: “Sensor Gain Fault Diagnosis for a Class of Nonlinear Systems”

The paper by Y. Wang and D. H. Zhou proposesa method to diagnose sensor gain faults for a class ofnonlinear systems. It classifies faults into two classes:the conditionally identifiable faults and the con-ditionally detectable faults. The authors also proposeanalgorithmtofindtheidentifiableandthedetectablefaults. An observer and an adaptive law aredesigned to estimate the attenuation coefficients

OBSERVER GAIN EFFECT IN LINEAR OBSERVER-BASED FAULT DETECTION

In linear observer-based fault detection methods, the observer gain plays an important role. Given a fixed detection threshold and the observer gain, the minimum detectable fault for a given type of fault is determined. In this paper, the effect of the observer gain on the time evolution of the residual sensitivity to a fault is analyzed. Then, using these sensitivity studies, the minimum detectable fault time evolution has been established. Three types of faults are introduced: permanently detected, non-permanently detected or just non-detected. Finally, an example based on a mineral grinding-classification process will be used to illustrate the results derived.