Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

Abstract

It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transition probabilities, instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. It is demonstrated that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits. The case where the circuit has a single scan chain, and the case where the circuit has multiple scan chains are considered.