Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

Abstract

A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains