Fault-tolerant Multiprocessor Research Articles

On evaluation of reliability increase in fault-tolerant multi processor systems

The work is devoted to the problem of evaluating the reliability increase of a fault-tolerant multiprocessor system by adding an extra processor to the system. It is assumed that the behavior of the modified system in the failure flow, in the case of the extra processor failure, does not differ from the behavior of the original system. The article describes both k-out-of-nsystems, and more complex ones, including hierarchical systems.An important feature of the proposed approach is that it involves the preliminary calculation of someadditionalauxiliaryvalues that do not depend on the reliability parameters of the added processor.Further, the reliability increase is assessed by substituting these parameter values into basicexpressions, which simplifies the selection of the optimal processor from the available set, sufficient to achieve the required level of system reliability, or confirms the impossibility of this.The proposed approach is compatible with any methods of calculating the reliability parameters of fault-tolerant multiprocessor systems but is particularly relevant for methods based on statistical experiments with models of system behavior in the failure flow, in particular, such as GL-models, due to the significant computational complexityof such calculations. In addition, for the simplest cases considered, k-out-of-nsystems with identical processors, a simple expression is proposed for an approximate estimateof the ratio of failure probabilities of the original and modified systems.Thehigher the reliability of the system processors, the higher the accuracy of such an assessment. Examples are given that prove the practical correctness of the proposed approaches.The calculation of the reliability system parameters, as well as auxiliary expressions, was based on conducting statistical experiments with corresponding GL-models.

S3QLRDF: distributed SPARQL query processing using Apache Spark—a comparative performance study

The proliferation of semantic data in the form of Resource Description Framework (RDF) triples demands an efficient, scalable, and distributed storage along with a highly available and fault-tolerant parallel processing strategy. There are three open issues with distributed RDF data management systems that are not well addressed altogether in existing work. First is the querying efficiency, second is that solutions are optimized for certain types of query patterns and don’t necessarily work well for all types, and third is concerned with reducing pre-processing cost. More precisely, the rapid growth of RDF data raises the need for an efficient partitioning strategy over distributed data management systems to improve SPARQL (SPARQL Protocol and RDF Query Language) query performance regardless of its pattern shape with minimized pre-processing time. In distributed RDF systems, both the data and the query processing are highly distributed. On the other hand, SPARQL workloads are dynamic and structurally diverse that can have different degrees of complexity. A complex SPARQL query over a large RDF graph in distributed systems requires combining a lot of distributed pieces of data through join operations. Therefore, designing an efficient data-partitioning schema and join strategy to minimize data transfer is the fundamental challenge in distributed RDF data management systems. In this context, we propose a new relational partitioning schema called Property Table Partitioning (PTP) for RDF data, that further partitions existing Property Table into multiple tables based on distinct properties (comprising of all subjects with non-null values for those distinct properties) in order to minimize input size and number of join operations of a query. This paper proposed a distributed RDF data management system called S3QLRDF, which is built on top of Spark and utilizes SQL to execute SPARQL queries over PTP schema. The experimental analysis with respect to preprocessing costs and query performance, using synthetic and real datasets shows that S3QLRDF outperforms state-of-the-art distributed RDF management systems.

Comments on “A Class of Fault-Tolerant Multiprocessor Networks”

A. Ghafoor presented node-disjoint paths of even networks using Figs. 4, 5, 6,and 7 (Ghafoor, IEEE Trans. Reliability, vol. 38, no. 1, pp. 5-15). However, the paper contains errors which cause confusion. We show that the node-disjoint paths, and Theorem 4 (Ghafoor, IEEE Trans. Reliability, vol. 38, no. 1, pp. 5-15), are not correct. We propose advanced node-disjoint paths, and prove that the fault diameter of even networks is <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> +1. This is optimal.

A fault-tolerant real-time multiprocessor with a built-in recovery mechanism

The architecture of a fault-tolerant multiprocessor with a rollback recovery mechanism is described. Fault-tolerance is attained owing to restarts of faulty processes of computations or their definite parts after detecting failures. An error occurring during the interaction of some processes leads to the multistep reconstruction of the entire computational process. An estimate of the efficiency of the proposed fault-tolerant technology is given.

Modeling and evaluating the time overhead induced by BER in COMA multiprocessors

Designing multiprocessors based on distributed shared memory (DSM) architecture considerably increases their scalability. But as the number of nodes in a multiprocessor increases, the probability of encountering failures in one or more nodes of the system raises as a serious problem. Thus, every large-scale multiprocessor should be equipped with mechanisms that tolerate node failures. Backward error recovery (BER) is one of the most feasible strategies to build fault tolerant multiprocessors and it can be shown that among various DSM-based architectures, cache only memory architecture (COMA) is the most suitable for implementing BER. The main reason is the existence of built-in mechanisms for data replication in COMA memory system. BER is applicable to COMA multiprocessors with minor hardware redundancy, but it will obviously cause some other kinds of overheads. The most important overhead induced by BER is the time required to produce and store recovery data. This paper introduces an analytical model for predicting the amount of this time overhead and then verifies the correctness of the model through comparing the results predicted from this model with the previously published simulation results. Both the analytical model and simulation results show that the overhead is nearly independent of the number of nodes. The immediate result is that BER is a cost-effective strategy for tolerating node failures in large-scale COMA multiprocessors with large numbers of nodes.

Systematic design of fault-tolerant multiprocessors with shared buses

A multiprocessor system is fault-tolerant (FT) if it preserves a fault-free subsystem of a predetermined interconnection structure when faults appear. We present a new method for designing FT multiprocessors that can efficiently tolerate both processor and interconnection faults. The approach is general, in that it can be applied to any multiprocessor topology. Shared buses serve as the main interconnection mechanism to minimize the switching logic needed for reconfiguration. We employ processor-bus-link (PBL) graphs to model multiprocessors with either dedicated or shared buses. Both processors and buses are represented as nodes so that bus faults can be considered explicitly and tolerated efficiently by spare buses instead of by spare processors. A minimum number of spare processors and buses are used to reduce hardware overhead. The node covering concept and the maximum-weight spanning tree algorithm are then employed to construct FT systems that have lower interconnection cost than most previous designs. We also present a cost-effective implementation method which is suitable for both static and dynamic reconfiguration techniques. The FT systems obtained have the advantages of no critical single point of failure, low redundancy, local replacement, and simple circuitry for fast reconfiguration.

The UltraSAN modeling environment

Model-based evaluation of computer systems and networks is an increasingly important activity. For modeling to be used effectively, software environments are needed that ease model specification, construction, and solution. Easy to use, graphical methods for model specification that support solution of families of models with differing parameter values are also needed. Since no model solution technique is ideal for all situations, multiple analysis and simulation-based solution techniques should be supported. This paper describes UltraSAN, one such software environment. The design of UltraSAN reflects its two main purposes: to facilitate the evaluation of realistic computer systems and networks, and to provide a test-bed for investigating new modeling techniques. In UltraSAN, models are specified using stochastic activity networks, a stochastic variant of Petri nets, using a graphical X-Window based interface that supports large-scale model specification, construction, and solution. Models may be parameterized to reduce the effort required to solve families of models, and a variety of analysis and simulation-based solution techniques are supported. The package has a modular organization that makes it easy to add new construction and solution techniques as they become available. In addition to describing the features, capabilities, and organization of UltraSAN, the paper illustrates the use of the package in the solution for the unreliability of a fault-tolerant multiprocessor using two solution techniques.

Design Issues for a Reconfigurable Fault-Tolerant Multiprocessor System Integrated in a CAM Environment

Abstract The paper proposes a shared-memory fault tolerant multiprocessor architecture for Computer Aided Manufacturing management and control, where an Ethernet LAN is used to connect FMC associated Station Computers to the shared memory residing in a supervising CAM server. Caches private to the processing elements together with caching protocols minimize the bottleneck effect of the LAN allowing for efficient parallel off- and on-line processing. A two-level Reconfigurable Switching Network allows for simple downloading of production data, programs and working orders. Using software redundancy, a fault-tolerant behaviour of the Station Computers Network is provided in order to reduce breaks in service of the manufacturing application at shop-floor level.

CSP methods for identifying atomic actions in the design of fault tolerant concurrent systems

Limiting the extent of error propagation when faults occur and localizing the subsequent error recovery are common concerns in the design of fault tolerant parallel processing systems. Both activities are made easier if the designer associates fault tolerance mechanisms with the underlying atomic actions of the system. With this in mind, the paper has investigated two methods for the identification of atomic actions in parallel processing systems described using CSP. Explicit trace evaluation forms the basis of the first algorithm, which enables a designer to analyze interprocess communications and thereby locate atomic action boundaries in a hierarchical fashion. The second method takes CSP descriptions of the parallel processes and uses structural arguments to infer the atomic action boundaries. This method avoids the difficulties involved with producing full trace sets, but does incur the penalty of a more complex algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cooperative Diagnosis and Routing in Fault-Tolerant Multiprocessor Systems

In this note, we consider the problem of fault-tolerant routing in multiprocessor systems when incomplete, or partial, diagnostic information is available. We first define a new type of partial diagnosis, known as k-reachability diagnosis. The overhead for k-reachability diagnosis increases with k, which specifies the radius of diagnostic information maintained by each node. We then present a routing algorithm, known as Algorithm Partial Route, that makes use of k-reachability diagnostic information and allows a trade-off between the amount of diagnostic information and the quality of routing. Partial Route is the first algorithm capable of handling systems of arbitrary topology containing an arbitrary number of faults. The worst-case performance of the algorithm in an n-node system, is shown to be optimal when k = n − 1 and within a factor of 2 of optimal when k = 1. Simulation results on meshes and hypercubes are also presented that show, in the average case, Algorithm Partial Route is nearly optimal for relatively small values of k.

Channel Multiplexing in Fault-Tolerant Modular Multiprocessors

A systematic approach to the design of fault-tolerant multiprocessors is described in this paper. This design approach utilizes the concept of multiplexing different channels of communication links to reconfigure fault-tolerant systems in the presence of faults. It is a simple approach which can be applied to different modular architectures and can implement different spare allocation strategies. In this paper, we derive the theoretical bounds of the channel requirement per link to reconfigure the system properly and utilize all the available spare nodes. For some links, this bound is as high as 2m, where m is the degree of a node. However, it is shown that a constant number of channels per link allows the system to be reconfigured properly and to utilize all the available spare nodes almost 100% of the time. We apply this approach to the construction of fault-tolerant binary trees and fault-tolerant binary hypercubes.

Some practical issues in the design of fault-tolerant multiprocessors

Methods for modeling and implementing various practical aspects of fault-tolerant multiprocessor systems largely neglected in prior research are examined. The node-covering design approach is generalized to accommodate systems whose structure and failure mechanisms are represented by arbitrary graphs. Several new types of covering graphs are defined, which lead to various useful design tradeoffs. A new technique for incremental design is presented, using a class of switch implementations that reduce a system's interconnection costs. The reduction of other cost factors is also addressed, and methods are presented for VLSI layout area minimization, fast and distributed reconfiguration, efficient transfer of state information for software recovery, and the efficient use of local spares.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dynamic fault-tree models for fault-tolerant computer systems

Reliability analysis of fault-tolerant computer systems for critical applications is complicated by several factors. Systems designed to achieve high levels of reliability frequently employ high levels of redundancy, dynamic redundancy management, and complex fault and error recovery techniques. This paper describes dynamic fault-tree modeling techniques for handling these difficulties. Three advanced fault-tolerant computer systems are described: a fault-tolerant parallel processor, a mission avionics system, and a fault-tolerant hypercube. Fault-tree models for their analysis are presented. HARP (Hybrid Automated Reliability Predictor) is a software package developed at Duke University and NASA Langley Research Center that can solve those fault-tree models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fault impact and fault tolerance in multiprocessor interconnection networks

Growing complexity of parallel machines coupled with increasing chip densities escalates the need for fault tolerance and recovery in these systems. In pursuit of the goal of fault-tolerant multiprocessors, many techniques have been proposed. Since methods for designing fault-tolerant processors and memories are relatively mature, the techniques considered in this paper focus on the interconnection network (ICN) linking the processors. The impact of faults on non-fault-tolerant ICNs is contrasted with that in fault-tolerant networks. Fault tolerance in ICNs is addressed at two levels, inter-node or switch level and system level. Inter-node or switch level pertains to data and control integrity and system level deals with maintaining network connectivity and adequate performance levels in the presence of faults. Fault-tolerant schemes at the switching element level warrant some form of concurrent error detection such as the use of codes usually combined with a full handshake protocol. Space–time trade-offs involved in the use of various codes and protocols are investigated. At the system level, several augmented multi-stage switching ICNs, tree and ring networks are studied. The combined provision for fault tolerance together with improved performance in the non-fault condition is emphasized. Finally, strategies for network reconfiguration and rerouting after system failure are presented.

A stable transactional memory for building robust object oriented programs

The purpose of the Fault Tolerant Multiprocessor project (FTM) is to design a fault tolerant machine based on a Stable Transactional Memory (STM). The STM allows manipulation of stable objects within atomic transactions. The building of the operating system has led us to define a C++ interface to the STM which provides stable classes. Robust object oriented programs which resist processor failures can be written in C++ using stable objects and transactions.

Automated analysis of phased-mission reliability

A method for automated analysis of phased mission reliability which considers the problem in terms of the construction of a continuous-time discrete-state Markov model and uses a standard Markov-chain solution technique that is adapted to the problem of phased missions is presented. The resulting state space is the union of the states in each independent phase, rather than the sum. This results in a model that can be substantially smaller than those required by other methods. A unified framework which is used for defining the separate phases using fault trees and for constructing and solving the resulting Markov model is discussed. The usual solution technique is altered to account for the phased nature of the problem. The framework is described for a previously published, simple three-component, three-phase system. An example in which a hypothetical two-phase application involving a fault-tolerant parallel processor is considered is given. The approach applies where the transition rates (failure and repair rates) are constant and where the phase change times are deterministic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Measurement and analysis of workload effects on fault latency in real-time systems

The authors demonstrate the need to address fault latency in highly reliable real-time control computer systems. It is noted that the effectiveness of all known recovery mechanisms is greatly reduced in the presence of multiple latent faults. The presence of multiple latent faults increases the possibility of multiple errors, which could result in coverage failure. The authors present experimental evidence indicating that the duration of fault latency is dependent on workload. A synthetic work generator is used to vary the workload, and a hardware fault injector is applied to inject transient faults of varying durations. This method makes it possible to derive the distribution of fault latency duration. Experimental results obtained from the fault-tolerant multiprocessor at the NASA Airlab are presented and discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modular fault tolerant VLSI parallel processor architectures with dynamic redundancy

In this paper a new Modular fault tolerant tree architecture for a VLSI Parallel processor is proposed. Modular fault tolerant Parallel processor architecture reliability analysis is presented. The proposed architecture significantly increases reliability and yield of the chip. Yield formulae are derived from the fundamentals of combinatorial and binomial methods for the Modular tree, RAE and SOFT tree architectures. Numerical results show that both the combinatorial and binomial analysis results are in good agreement. Furthermore, the derived yield formulae are used to get first hand information about a specific VLSI architecture, which is sultable for manufacturing or not. Finally, the figure of merlt shows that Modular fault tolerant Parallel processor architecture is cost effective in terms of the chip yield.

Comments, on "Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks" by Y.-H. Lee and K.G. Shin

The author shows that formula (9) of the above mentioned paper (see ibid., vol.C-33, p.113-124, (1984)) is erroneous. A new solution is proposed, and its congruency is shown. >

An operating system for a fault-tolerant multiprocessor controller

The development of an operating system that is a central component of a fault-tolerant multiprocessor is described. The operating system, while relatively simple and small, supports multitasking and multiprocessing, as well as both self-diagnostics and cross-diagnostics for fault detection. In the event of a fault, the system permits rapid reconfiguration in a manner that retains processing for the highest-priority tasks. Since the hardware needed to provide fault tolerance is available when there are no faults, the operating system can utilize this excess capacity to accomplish lower-priority tasks during normal operation. This approach yields graceful degradation in response to faults in the system components.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>