Fault-tolerant Memory Research Articles

High-threshold and low-overhead fault-tolerant quantum memory

The accumulation of physical errors1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm5. We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes6. Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length-n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.

Quantum error correction of spin quantum memories in diamond under a zero magnetic field

Fault-tolerant quantum memory plays a key role in interfacing quantum computers with quantum networks to construct quantum computer networks. Manipulation of spin quantum memory generally requires a magnetic field, which hinders the integration with superconducting qubits. Completely zero-field operation is desirable for scaling up a quantum computer based on superconducting qubits. Here we demonstrate quantum error correction to protect the nuclear spin of the nitrogen as a quantum memory in a diamond nitrogen-vacancy center with two nuclear spins of the surrounding carbon isotopes under a zero magnetic field. The quantum error correction makes quantum memory resilient against operational or environmental errors without the need for magnetic fields and opens a way toward distributed quantum computation and a quantum internet with memory-based quantum interfaces or quantum repeaters.

A New Nano-Design of a Fault-Tolerant Coplanar RAM with Set/Reset Ability Based on Quantum-Dots

Quantum Dot Cellular Automata (QCA) is a recent technology that has piqued researchers’ interest because of its small size and low energy consumption. With the help of quantum dots, the QCA technology delivers a new computational foundation for constructing digital circuits. Medical imaging and quantum computing are just a few applications for quantum dots. Quantum dots are nanocrystals that transmit data at the nano-scale. Since the memory is an important digital circuit, this work proposes a fault-tolerant loop-based coplanar Random Access Memory (RAM) with set/reset capability that uses the QCA rules. The memory cell’s operation is verified both physically and through simulations with the QCADesigner program. The quantum cost of the proposed memory cell shows that it has a negligible quantum cost. The proposed QCA-based memory circuit performs well in simulations, with 96 QCA cells and the output signal generated after 0.75 clock phases. The gates and wire in this design have around 85 percent better fault-tolerant capability than the best-presented memory systems. Furthermore, this circuit can tolerate most cell omission, displacement, misalignment, and deposition faults. This structure can be used to create high-performance higher-order fault-tolerant memory structures.

Implementation of Memory in a System on a Chip with Built-In Self-Testing and Self-Healing

When manufacturing systems on a chip using modern technologies with highly integrated elements, problems arise in testing and repairing the internal memory. The original architecture of the fault-tolerant semiconductor memory with the given failure detection rate is proposed. At the same time, rather than the entire device being backed up only the elements that are most susceptible to failures are backed up, which reduces its weight and cost. The fault-tolerant memory design with automatic recovery is verified after quadruple failures. The fault-tolerant memory project is implemented in the M2S010-TQ144 chip of the system based on the SF2-Junior-KIT chip in the integrated development environment of Microsemi Libero SoC v11.8. The proposed architecture of fault-tolerant memory ensures the automatic recovery from the multiple failures of elements onboard spacecraft control systems using a built-in self-healing device without the use of fusible jumpers and the participation of maintenance personnel. In the semiconductor memory, when faults are detected, the data bits of the main array of storage cells in which failures occur are automatically replaced with the data emerging from the outputs of the spare array of storage cells. This improves reliability when performing multiple recovery cycles.

Fault-tolerant H∞ filtering for fuzzy networked control systems with quantisation effects

ABSTRACTThe issue of memory filter design is investigated for a class of discrete-time Takagi–Sugeno (T-S) fuzzy networked control systems with time-varying delay and quantisation effects. The main objective of this paper is to formulate an memory filter that can guarantee the resulting filtering error system to be finite-time bounded. Further, by considering the communication limitations, the state signals are quantised before transmission through a logarithmic quantiser and the quantisation error is considered in the filter design. In particular, the quantisation effects are dealt by employing the generalised sector bound approach. Based on Lyapunov stability theory, novel sufficient constraints are established in the form of linear matrix inequalities, to ensure the finite-time boundedness of the augmented filtering error system. Then, a new fault-tolerant memory filter is formulated and also the filter gain parameters are attained by solving the derived LMI based constraints. Finally, a numerical example is furnished to support the efficacy and applicability of the developed filter design.

Implementation and Analysis of Methods for Error Detection and Correction on FPGA

In this paper, two methods are implemented and analyzed on a Field Programable Gate Array (FPGA) board for the design of fault-tolerant pipelined sequential and combinational circuits. Evaluated methods are named Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC). The mentioned methods are based on Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant master-slave flip-flops with fault tolerant memory elements. Additional to the analysis and implementation of the methods, the enhancement to a method is proposed.

Fault-Tolerant and Deterministic Flight-Software System For a High Performance CubeSat

We describe the design and implementation of a complete flight-software operating system (OS) for a high-performance CubeSat carrying a third-party payload. This CubeSat's mission is to carry out research experiments on this payload while in low earth orbit. These experiments may be specified and prepared on the ground while the CubeSat is already in flight, and later uploaded via communication link. Experimental results collected by the CubeSat may likewise be downloaded to the ground. The CubeSat must collect and respond to sensor telemetry every second, and respond to ground communication on demand. To survive an adversarial space environment, the CubeSat OS is implemented as a deterministic state machine, storing state in a fault tolerant global memory structure. We validate our system via an end to end test of the CubeSat with its ground station, and demonstrate its capability to tolerate and even actively mitigate potential faults resulting from space radiation.

Enhanced architectures for soft error detection and correction in combinational and sequential circuits

In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.

FAULT TOLERANT MEMORY SYSTEM WITH ACTIVE REDUNDANCY FOR CRITICAL APPLICATIONS

This paper proposes a fault tolerant RAM memory architecture with active redundancy dedicated to critical applications. To assure high reliability, additional modules are provided in the system. To reach a high safety, memory system is composed by built-in self-testing RAM devices (BIST?RAM). Memory modules are tested online one by one, in a sequential order, during the normal operation. A primary module under testing is temporary replaced by another one. If one module is diagnosed as being failed it is eliminated from the system automatically and replaced with a spare module. The memory control unit responsible for performing the reconfiguration of the memory system has a cellular structure and introduces an acceptable extra delay for the memory access.

Fault Tolerant Design for Magnetic Memories

This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and tested with Fault Injection Circuits and ATPG effectiveness was found out to be 100% at a frequency of 500 MHZ.

Optimal Bacon-Shor codes

We study the performance of Bacon-Shor codes, quantum subsystem codes which are well suited for applications to fault-tolerant quantum memory because the error syndrome can be extracted by performi...

Fault-tolerant design of spaceborne mass memory system

A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components. The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure. Error correcting code (ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset. For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/s. In space environment, ECC combined with periodical scrubbing is appropriate and it reduces the word error rate by 5 orders of magnitude with 1% timing overhead and small hardware expenditure.

Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits

Critical defects, i.e., faults, inevitably occur during semiconductor fabrication, and they significantly reduce both manufacturing yield and product reliability. To decrease the effects of the defects, several fault-tolerance methods, such as the redundancy technique and the error correcting code (ECC), have been successfully applied to memory integrated circuits. In the semiconductor business, accurate estimation of yield and reliability is very important for determining the chip architecture as well as the production plan. However, a simple conjunction of previous fault-tolerant yield models tends to underestimate the manufacturing yield if several fault-tolerance techniques are employed simultaneously. This paper concentrates on developing and verifying an accurate yield model which can be applied successfully in such situations. The proposed conjunction model has been derived from the probability of remaining redundancies and the average number of defects after repairing the defects with the remaining redundancies. The validity of the conjunction yield model is verified by a Monte Carlo simulation.

Soft error recovery in simplex and triplex memory systems

This paper analyzes and compares the reliability and MTTF of four fault-tolerant memory configurations subject to soft errors, namely (i) the SEC protected RAM (SEC-RAM), (ii) the SEC-unprotected triplex RAM (TMR-RAM), (iii) the triplex SEC-protected RAM (TMR-SEC RAM) and (iv) the SEC-protected triplex RAM (SEC-TMR RAM). The last two configurations are new and their difference lies on the order of performing the voting and decoding operations. Depending on the configuration, memory modeling is accomplished by Markov models either at the bit or at the word level, by also taking into account the canceling of soft errors due to subsequent soft errors. Exact theoretical expressions for the reliability and MTTF of the SEC-RAM and TMR-RAM are developed and two alternative recursive algorithms are given to assess the impact of memory scrubbing on MTTF. The advantage of both the proposed configurations is that they can tolerate all possible error patterns with three errors and they also present a remarkable resistance to error patterns with a much larger number of errors. As the analysis of the SEC-TMR RAM cannot be accomplished theoretically, due to the varying error-patterns of the SEC decoder output for more than one error in a codeword, a fast error-pattern generation algorithm (FEP) is developed. Simulation results show that there exist numerous multiple-bit error patterns in more than two words in the SEC-TMR RAM that upon decoding and voting produce the correct data-word. A comparison of the multiple-bit error masking capability of the TMR-SEC and SEC-TMR is also given.

An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes

In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.

Fault Tolerance Techniques for High Capacity RAM

As the complexity and size of the embedded memories keep increasing, improving the yield of embedded memories is the key step toward improving the overall chip yield of a SOC design. The most well known way to improve the memory yield is by using redundant elements to replace the faulty cells. However, the repair efficiency mainly depends on the type, and the amount of redundancy; and on the redundancy analysis algorithms. Therefore, new types of redundancy based on divided bit-line (DBL), and divided word-line (DWL) techniques are proposed in this work. A memory column (row), including the redundant column (row), is partitioned into column blocks (row blocks), respectively. A row/column block is used as the basic replacement element instead of a row/column for the traditional approaches. Based on the new types of redundancy, three types of fault-tolerant memory (FTM) systems are also proposed. If a redundant row/column block is used as the basic replacement element, then the row block-based FTM (RBFTM)/column block-based (CBFTM) system is used. If both the DWL, and DBL techniques are implemented onto a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) block. To achieving better repair efficiency, a novel hybrid block-repair (HBR) algorithm is also proposed. This algorithm is suitable for hardware implementation with negligible overhead. For the HFTM system, the hardware overheads are less than 0.65%, and 0.7% for 64-Kbit SRAM, and 8-Mbit DRAM, respectively. Moreover, the repair rate can be improved significantly. Experimental results show that our approaches can improve the memory fabrication yield significantly. The characteristics of low power and fast access time of DBL and DWL techniques are also preserved.

Reliability Measurement of Mass Storage System for Onboard Instrumentation

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are the commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments, such as extreme radiation, can be experienced throughout the mission. Acceptable dependability for these instruments has been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering . This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a reliable foundation of measurement. Then, lifelong dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of the reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (i.e., the expected time that a system will operate before it fails). Finally, minimal column redundancy search technique for the fault-tolerant memory system is proposed and verified through a series of parametric simulations. Thereby, design and fabrication of cost-effective and highly reliable fault-tolerant onboard mass storage system can be realized for dependable instrumentation.

Structural Complexity of Fault-Tolerant Memory for Computerized Measurement Systems

Estimates are made of the hardware costs and functional reliability of a structural model for a fault-tolerant memory for computerized measuring instruments, which realizes an error-correcting code providing correction of errors of a given multiplicity and the detection of the maximum number of uncorrectable errors.

On model checking data-independent systems with arrays without reset

A system is data-independent with respect to a data type $X$ iff the operations it can perform on values of type $X$ are restricted to just equality testing. The system may also store, input and output values of type $X$. We study model checking of systems which are data-independent with respect to two distinct type variables $X$ and $Y$, and may in addition use arrays with indices from $X$ and values from $Y$. Our main interest is the following parameterised model-checking problem: whether a given program satisfies a given temporal-logic formula for all non-empty finite instances of $X$ and $Y$. Initially, we consider instead the abstraction where $X$ and $Y$ are infinite and where partial functions with finite domains are used to model arrays. Using a translation to data-independent systems without arrays, we show that the $\mu$-calculus model-checking problem is decidable for these systems. From this result, we can deduce properties of all systems with finite instances of $X$ and $Y$. We show that there is a procedure for the above parameterised model-checking problem of the universal fragment of the $\mu$-calculus, such that it always terminates but may give false negatives. We also deduce that the parameterised model-checking problem of the universal disjunction-free fragment of the $\mu$-calculus is decidable. Practical motivations for model checking data-independent systems with arrays include verification of memory and cache systems, where $X$ is the type of memory addresses, and $Y$ the type of storable values. As an example we verify a fault-tolerant memory interface over a set of unreliable memories.

Lazy garbage collection of recovery state for fault-tolerant distributed shared memory

In this paper, we address the problem of garbage collection in a single-failure fault-tolerant home-based lazy release consistency (HLRC) distributed shared-memory (DSM) system based on independent checkpointing and logging. Our solution uses laziness in garbage collection and exploits consistency constraints of the HLRC memory model for low overhead and scalability. We prove safe bounds on the state that must be retained in the system to guarantee correct recovery after a failure. We devise two algorithms for garbage collection of checkpoints and logs, checkpoint garbage collection (CGC), and lazy log trimming (LLT). The proposed approach targets large-scale distributed shared-memory computing on local-area clusters of computers. In such systems, using global synchronization or extra communication for garbage collection is inefficient or simply impractical due to system scale and temporary disconnections in communication. The challenge lies in controlling the size of the logs and the number of checkpoints without global synchronization while tolerating transient disruptions in communication. Our garbage collection scheme is completely distributed, does not force processes to synchronize, does not add extra messages to the base DSM protocol, and uses only the available DSM protocol information. Evaluation results for real applications show that it effectively bounds the number of past checkpoints to be retained and the size of the logs in stable storage.