Implementation of Memory in a System on a Chip with Built-In Self-Testing and Self-Healing

Abstract

When manufacturing systems on a chip using modern technologies with highly integrated elements, problems arise in testing and repairing the internal memory. The original architecture of the fault-tolerant semiconductor memory with the given failure detection rate is proposed. At the same time, rather than the entire device being backed up only the elements that are most susceptible to failures are backed up, which reduces its weight and cost. The fault-tolerant memory design with automatic recovery is verified after quadruple failures. The fault-tolerant memory project is implemented in the M2S010-TQ144 chip of the system based on the SF2-Junior-KIT chip in the integrated development environment of Microsemi Libero SoC v11.8. The proposed architecture of fault-tolerant memory ensures the automatic recovery from the multiple failures of elements onboard spacecraft control systems using a built-in self-healing device without the use of fusible jumpers and the participation of maintenance personnel. In the semiconductor memory, when faults are detected, the data bits of the main array of storage cells in which failures occur are automatically replaced with the data emerging from the outputs of the spare array of storage cells. This improves reliability when performing multiple recovery cycles.