Fault-tolerant Processing Research Articles

A distributed image-retrieval method in multi-camera system of smart city based on cloud computing

In smart city, accurate video sensing information is very critical for the whole city system. However, huge amount of information is the main characteristic of multi-camera system, and we have truly been in big data era for image/video processing. In the development of modern smart city, how to make accurate image retrieval in multi-camera system should be considered seriously. In previous researches, many approaches have been put forward. To the best of our knowledge, there is few research focusing on the method based on distributed fault-tolerant processing (DFP) method. The introduction of DFP will greatly improve the processing rate based on cloud computing, so it will be beneficial to the improvement of this issue. In this paper, we propose a distributed image-retrieval method designed for cloud-computing based multi-camera system in smart city. Through the combination of the cloud storage technology, data encryption and data retrieval technology, we achieve efficient integration and management of multi-camera resources. In this way, the cloud computing network data will be released more quickly, which can provide convenient storage service for users. What is more, experimental results show the scalability and effectiveness of the proposed method, compared with previous processing methods.

80 μW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

80 μW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

High-Fidelity Universal Gate Set for ^{9}Be^{+} Ion Qubits.

We report high-fidelity laser-beam-induced quantum logic gates on magnetic-field-insensitive qubits comprised of hyperfine states in ^{9}Be^{+} ions with a memory coherence time of more than 1s. We demonstrate single-qubit gates with an error per gate of 3.8(1)×10^{-5}. By creating a Bell state with a deterministic two-qubit gate, we deduce a gate error of 8(4)×10^{-4}. We characterize the errors in our implementation and discuss methods to further reduce imperfections towards values that are compatible with fault-tolerant processing at realistic overhead.

Model prototype utilization in the analysis of fault tolerant control and data processing systems

The procedure assessing the profit of control and data processing system implementation is presented in the paper. The reasonability of model prototype creation and analysis results from the implementing of the approach of fault tolerance provision through the inclusion of structural and software assessment redundancy. The developed procedure allows finding the best ratio between the development cost and the analysis of model prototype and earnings from the results of this utilization and information produced. The suggested approach has been illustrated by the model example of profit assessment and analysis of control and data processing system.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.

Evaluation of Fault Tolerance in Cloud Computing using Colored Petri Nets

Nowadays, the necessity of rendering reliable services to the customers in business markets is assumed as a crucial matter for the service providers, and the importance of this subject in many fields is undeniable. Design of systems with high complexity and existence of different resources in network cloud leads the service providers to intend to provide the best services to their customers. One of the important challenges for service providers is fault tolerance and reliability and different techniques and methods have been presented for solving this challenge so far. The method presented in this paper analyzes the fault tolerance process in interconnected network cloud in order to avoid problems and irreparable damages before implementation. In the offered method, the fault tolerance was evaluated aiding colored petri nets using Byzantine technique. Summary of results analyzed by cpntools and demonstrated reliability. It was concluded that upon increase of requests, the fault tolerance is reduced and consequently reliability is also reduced and vice versa. In other word, resources management is under impact of requested services.

HANDLING MULTIPLE FAILURES IN PROCESS NETWORKS

Process network is a computation model used in digital signal processing. This model is effective for solving various tasks, which can be divided into multiple concurrent processes. These processes communicate through unbounded FIFO buffers and can be executed simultaneously. In real time digital signal processing applications execution time is often infinite. However, various hardware/software failures can occur. These failures can be single or multiple. In our work, dynamic run-time reconfiguration is introduced into process network which ensures single or multiple error handling, avoiding deadlocks, continuous and on-time result delivery. In this paper, we extend Fault Tolerant Process Network with algorithm for avoiding multiple simultaneous failures, which is also suitable for avoiding a single failure.

Securing data exchange in wireless multimedia sensor networks: perspectives and challenges

The emerging use of Wireless Multimedia Sensor Networks (WMSNs) and communication facilities have increased the need for network security measures to protect different types of multimedia data either real time or non-real time during the transmission period. A lot of researchers are becoming more interested on secure WMSNs due to the broad application necessities which can be range over smart environment, security surveillance and smart health-care; so requirements on secure aggregation of multimedia data, Quality of Service (QoS) and privacy should be satisfied. Current technologies vs. proposed security techniques in WMSNs and its pros and cons from a security point of view are explored in details. In addition to promising future trends of this research area by giving more attention for new challenging problems including secure routing protocol, fault tolerant, robustness and recovery process. We believe that this paper will add significantly a valuable discussion among the researchers and promote them to fetch new research ideas to design approximately best model by combining the most important security issues in order to reach secure WMSNs.

Software Reliability Validation and Verification Using Fault Injection Techniques on a Fault Tolerant Processor

Due to the continuously increasing complexities of embedded electronic systems, there is a clear need for more sophisticated methods of testing and evaluating the performances and reliabilities of the embedded software. One such method is to simulate potentially dangerous events, while monitoring the system's response and stability. This paper presents a software simulation tool, which will be used for evaluating the mission critical software of the TRISAT mission. The software simulation tool simulates, on a per-cycle basis, the fault tolerant processor and its peripherals while also simulating the effects of the space environment on the simulated hardware. Using the simulation software, a dependability analysis was performed regarding the use of Error Correction and Detection Codes on the processor data memory as well as the rate of memory scrubbing, using two benchmark algorithms: matrix multiplication and quick sort.

Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing

Fault tolerant techniques can extend the power savings achievable by dynamic voltage scaling by trading accuracy and/or timing performance against power. Such energy improvements have a strong dependency on the delay distribution of the circuit and the statistical characteristics of the input signal. Independently, programmable truncated multipliers also achieve power benefits at the expense of degradation of the output signal-to-noise ratio. In this brief, a combination of programmable truncated multiplication is used within a fault tolerant digital signal processing (DSP) structure in which the supply voltage is reduced beyond the critical timing level. Timing modulation properties of truncated multiplication are analyzed and demonstrated to improve the performance of fault tolerant designs, reducing error correction burdens, and extending the system operating voltage range. Combining both power strategies results in lower energy consumption levels, which improve the energy savings beyond that expected when applying a combination of both techniques with the original DSP.

A Flexibly Fault-Tolerant FU Array Processor and its Self-Tuning Scheme to Locate Permanently Defective Unit

Nowadays, small feature-sized transistors and wires led by the process miniaturization have shown increasing vulnerability to both transient and permanent faults. Modular redundancy in circuits and failure-unit isolation are thereby employed to guarantee the correct execution and also to well keep the lifespan of electronic devices. In this work, we propose the Explicit Redundancy Linear Array (EReLA) architecture to provide a highly flexible fault tolerance. EReLA follows the baseline reconfigurable architecture, which works best with failure-unit isolation and hot-swap techniques. In addition, specifically for the preparation of hot swaps, we propose a low-cost self-tuning scheme, to fast locate the precise position of the defective processing element or network connection. Powered by these schemes, EReLA is functionally the same as a traditional TMR processor in terms of fault tolerance, while the power data of a 180nm prototype EReLA chip has indicated that it incurs about 1/3 less power consumption than the TMR implementation.

Improved fault tolerance of Turbo decoding based on optimized index assignments

Abstract. This paper investigates the impact of an error-prone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

Exception Throwing Analysis and Exception Handling Method for BPEL

Business developer needs to develop fault-tolerant process, but fault-tolerant process development based on exception handling mechanism provided by BPEL costs much time and is easy to make mistake. We analyze application exception throw chain theory of service-oriented system. Exception throwing of BPEL process is broadcasted among component layer, service layer and process layer. We also propose an application exception handling method for BPEL by using EHPDL-P. EHPDL-P can separate normal business logic and exception business logic, and thus it can enhance BPEL fault-tolerance ability.

FPGA Based Fault Tolerance and Recovery Process in Digital Systems Using Genetic Algorithm

FPGA Based Fault Tolerance and Recovery Process in Digital Systems Using Genetic Algorithm

FPGA Based Fault Tolerance and Recovery Process in Digital Systems Using Genetic Algorithm

FPGA Based Fault Tolerance and Recovery Process in Digital Systems Using Genetic Algorithm

PID Adaptive Control in the Application of the Induction Motor System Based on the RBF Neural Network Inverse

In view of the nonlinear mapping ability of artificial neural network, the ability of self-learning and adaptive uncertainty system dynamic characteristic, fault tolerant and generalization ability and parallel processing ability, etc., the article puts forward a PID adaptive control algorithm based on neural network inverse as well, introducing RBF neural network to the inverse control, and operating PID integration. In a sudden external disturbance and model parameter change, the control scheme can significantly reduce resistance perturbation influence on speed, and strong robustness on parameter variations and external disturbances of the system.

Analysis and Simulation on Clock Resynchronization in Time Triggered Architecture

An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.

A Design for Fault-Tolerant Communication Middleware Based on Time-Triggered

Against to the unsustainable problems of health diagnosis, fault location and fault tolerance mechanisms that existing in the current avionics applications, we proposed a fault-tolerant communication middleware which is based on time-triggered in this paper. This middleware is designed to provide a support platform for applications of the real-time based on communication middleware. From the communication middleware level and also combined with time-triggered mechanism and fault-tolerant strategy, it diagnoses the general faults first, and then routes them to the appropriate fault mechanism to process it. So the middleware completely separates fault-tolerant process from the application software functions.

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project

Modern embedded systems increasingly require adaptive run-time management of available resources. One method for supporting adaptivity is to implement run-time application mapping. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance the computing load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots, and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focused particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults.In this paper, we summarize the major results achieved in the MADNESS project regarding the system adaptivity and fault-tolerant processing. We report the results of the integration between platform level and middleware level support for adaptivity and fault-tolerance. Two case studies demonstrate the survival ability of the system via a low-overhead process migration mechanism and by taking near optimal remapping decisions at run-time.