Abstract
Nowadays, small feature-sized transistors and wires led by the process miniaturization have shown increasing vulnerability to both transient and permanent faults. Modular redundancy in circuits and failure-unit isolation are thereby employed to guarantee the correct execution and also to well keep the lifespan of electronic devices. In this work, we propose the Explicit Redundancy Linear Array (EReLA) architecture to provide a highly flexible fault tolerance. EReLA follows the baseline reconfigurable architecture, which works best with failure-unit isolation and hot-swap techniques. In addition, specifically for the preparation of hot swaps, we propose a low-cost self-tuning scheme, to fast locate the precise position of the defective processing element or network connection. Powered by these schemes, EReLA is functionally the same as a traditional TMR processor in terms of fault tolerance, while the power data of a 180nm prototype EReLA chip has indicated that it incurs about 1/3 less power consumption than the TMR implementation.
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