Improved fault tolerance of Turbo decoding based on optimized index assignments

J Geldmacher,J Götze

doi:10.5194/ars-12-187-2014

Abstract

Abstract. This paper investigates the impact of an error-prone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

Highlights

Two impact factors for the power consumption of a signal processing circuit can be identified: Power consumption of the logic and power consumption of the involved buffer memory
This paper investigates the impact of an errorprone buffer memory on a channel decoder as employed in modern digital communication systems
If relaxing quality requirements in a controlled fashion, significant energy reduction can be achieved: In aggressive voltage scaling (AVS) (Hegde and Shanbhag, 2001; Djahromi et al, 2007; Makhzan et al, 2007), the supply voltage of an embedded circuit is deliberately reduced below the required threshold

Summary

Introduction

Two impact factors for the power consumption of a signal processing circuit can be identified: Power consumption of the logic (roughly related to the algorithmic complexity) and power consumption of the involved buffer memory. Yoshimoto et al (2012) It has been recognized (Shanbhag et al, 2010; Mitra et al, 2010; Karakonstantis et al, 2012; Kleeberger et al, 2013), that the development of fault tolerant (error resilient) systems cannot be dealt with in a single perspective, but rather that a crosslayer view is required: A co-design of embedded circuits and signal-processing algorithms will be necessary to efficiently exploit potentials of approaches like AVS and to obtain relatively reliable systems based on unreliable underlying components. It is shown that joint optimization of index assignment and quantizer can significantly improve error-resilience of the decoder, without increasing its computational complexity

System model

Characteristics of memory channel

Findings

Conclusions