Family Of Circuits Research Articles

Exploring Entanglement and Optimization within the Hamiltonian Variational Ansatz

Quantum variational algorithms are one of the most promising applications of near-term quantum computers; however, recent studies have demonstrated that unless the variational quantum circuits are configured in a problem-specific manner, optimization of such circuits will most likely fail. In this paper, we focus on a special family of quantum circuits called the Hamiltonian Variational Ansatz (HVA), which takes inspiration from the quantum approximation optimization algorithm and adiabatic quantum computation. Through the study of its entanglement spectrum and energy gradient statistics, we find that HVA exhibits favorable structural properties such as mild or entirely absent barren plateaus and a restricted state space that eases their optimization in comparison to the well-studied "hardware-efficient ansatz." We also numerically observe that the optimization landscape of HVA becomes almost trap free when the ansatz is over-parameterized. We observe a size-dependent "computational phase transition" as the number of layers in the HVA circuit is increased where the optimization crosses over from a hard to an easy region in terms of the quality of the approximations and speed of convergence to a good solution. In contrast with the analogous transitions observed in the learning of random unitaries which occur at a number of layers that grows exponentially with the number of qubits, our Variational Quantum Eigensolver experiments suggest that the threshold to achieve the over-parameterization phenomenon scales at most polynomially in the number of qubits for the transverse field Ising and XXZ models. Lastly, as a demonstration of its entangling power and effectiveness, we show that HVA can find accurate approximations to the ground states of a modified Haldane-Shastry Hamiltonian on a ring, which has long-range interactions and has a power-law entanglement scaling.

Efficient simulatability of continuous-variable circuits with large Wigner negativity

Discriminating between quantum computing architectures that can provide quantum advantage from those that cannot is of crucial importance. From the fundamental point of view, establishing such a boundary is akin to pinpointing the resources for quantum advantage; from the technological point of view, it is essential for the design of non-trivial quantum computing architectures. Wigner negativity is known to be a necessary resource for computational advantage in several quantum-computing architectures, including those based on continuous variables (CVs). However, it is not a sufficient resource, and it is an open question under which conditions CV circuits displaying Wigner negativity offer the potential for quantum advantage. In this work we identify vast families of circuits that display large, possibly unbounded, Wigner negativity, and yet are classically efficiently simulatable, although they are not recognized as such by previously available theorems. These families of circuits employ bosonic codes based on either translational or rotational symmetries (e.g., Gottesman-Kitaev-Preskill or cat codes), and can include both Gaussian and non-Gaussian gates and measurements. Crucially, within these encodings, the computational basis states are described by intrinsically negative Wigner functions, even though they are stabilizer states if considered as codewords belonging to a finite-dimensional Hilbert space. We derive our results by establishing a link between the simulatability of high-dimensional discrete-variable quantum circuits and bosonic codes.

Power of uninitialized qubits in shallow quantum circuits

We study uninitialized qubits, whose initial state is arbitrary and unknown, in relation to the computational power of shallow quantum circuits. To do this, we consider uniform families of shallow quantum circuits with n input qubits, O(log⁡n) initialized ancillary qubits, and nO(1) uninitialized ancillary qubits, where the input qubits only act as control qubits. We show that such a circuit with depth O((log⁡n)2) can compute any symmetric Boolean function on n bits that is computable by a uniform family of polynomial-size classical circuits. Since it is unlikely that this can be done with only O(log⁡n) initialized ancillary qubits, our result provides evidence that the presence of uninitialized ancillary qubits increases the computational power of shallow quantum circuits with only O(log⁡n) initialized ancillary qubits. On the other hand, to understand the limitations of uninitialized qubits, we focus on sub-logarithmic-depth quantum circuits and show the impossibility of computing the parity function on n bits.

A Low-Waste Reliable Adiabatic Platform

Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome observations, we have proposed LWRAP, a fault tolerant circuit design for dual-rail adiabatic families. While improving the reliability, LWRAP employs the well-known dynamic frequency scaling approach for mitigating the amount of imposed energy overhead in the design. Our precise SPICE simulations have shown that LWRAP improves the reliability of the circuit against transient faults by up to 12x, depending on the technology size.

A volumetric framework for quantum computer benchmarks

We propose a very large family of benchmarks for probing the performance of quantum computers. We call them {volumetric benchmarks} (VBs) because they generalize IBM's benchmark for measuring quantum volume \cite{Cross18}. The quantum volume benchmark defines a family of {square} circuits whose depth d and width w are the same. A volumetric benchmark defines a family of {rectangular} quantum circuits, for which d and w are uncoupled to allow the study of time/space performance trade-offs. Each VB defines a mapping from circuit shapes -- (w,d) pairs -- to test suites C(w,d). A test suite is an ensemble of test circuits that share a common structure. The test suite C for a given circuit shape may be a single circuit C, a specific list of circuits {C1…CN} that must all be run, or a large set of possible circuits equipped with a distribution Pr(C). The circuits in a given VB share a structure, which is limited only by designers' creativity. We list some known benchmarks, and other circuit families, that fit into the VB framework: several families of random circuits, periodic circuits, and algorithm-inspired circuits. The last ingredient defining a benchmark is a success criterion that defines when a processor is judged to have ``passed'' a given test circuit. We discuss several options. Benchmark data can be analyzed in many ways to extract many properties, but we propose a simple, universal graphical summary of results that illustrates the Pareto frontier of the d vs w trade-off for the processor being benchmarked.

A SCHEMATIC DEFINITION OF QUANTUM POLYNOMIAL TIME COMPUTABILITY

AbstractIn the past four decades, the notion of quantum polynomial-time computability has been mathematically modeled by quantum Turing machines as well as quantum circuits. This paper seeks the third model, which is a quantum analogue of the schematic (inductive or constructive) definition of (primitive) recursive functions. For quantum functions mapping finite-dimensional Hilbert spaces to themselves, we present such a schematic definition, composed of a small set of initial quantum functions and a few construction rules that dictate how to build a new quantum function from the existing ones. We prove that our schematic definition precisely characterizes all functions that can be computable with high success probabilities on well-formed quantum Turing machines in polynomial time, or equivalently uniform families of polynomial-size quantum circuits. Our new, schematic definition is quite simple and intuitive and, more importantly, it avoids the cumbersome introduction of the well-formedness condition imposed on a quantum Turing machine model as well as of the uniformity condition necessary for a quantum circuit model. Our new approach can further open a door to the descriptional complexity of quantum functions, to the theory of higher-type quantum functionals, to the development of new first-order theories for quantum computing, and to the designing of programming languages for real-life quantum computer

Scrambling in random unitary circuits: Exact results

We study the scrambling of quantum information in local random unitary circuits by focusing on the tripartite information proposed by Hosur et al. We provide exact results for the averaged R\'enyi-$2$ tripartite information in two cases: (i) the local gates are Haar random and (ii) the local gates are dual-unitary and randomly sampled from a single-site Haar-invariant measure. We show that the latter case defines a one-parameter family of circuits, and prove that for a "maximally chaotic" subset of this family quantum information is scrambled faster than in the Haar-random case. Our approach is based on a standard mapping onto an averaged folded tensor network, that can be studied by means of appropriate recurrence relations. By means of the same method, we also revisit the computation of out-of-time-ordered correlation functions, re-deriving known formulae for Haar-random unitary circuits, and presenting an exact result for maximally chaotic random dual-unitary gates.

Collective Computation in Animal Fission-Fusion Dynamics.

Recent work suggests that collective computation of social structure can minimize uncertainty about the social and physical environment, facilitating adaptation. We explore these ideas by studying how fission-fusion social structure arises in spider monkey (Ateles geoffroyi) groups, exploring whether monkeys use social knowledge to collectively compute subgroup size distributions adaptive for foraging in variable environments. We assess whether individual decisions to stay in or leave subgroups are conditioned on strategies based on the presence or absence of others. We search for this evidence in a time series of subgroup membership. We find that individuals have multiple strategies, suggesting that the social knowledge of different individuals is important. These stay-leave strategies provide microscopic inputs to a stochastic model of collective computation encoded in a family of circuits. Each circuit represents an hypothesis for how collectives combine strategies to make decisions, and how these produce various subgroup size distributions. By running these circuits forward in simulation we generate new subgroup size distributions and measure how well they match food abundance in the environment using transfer entropies. We find that spider monkeys decide to stay or go using information from multiple individuals and that they can collectively compute a distribution of subgroup size that makes efficient use of ephemeral sources of nutrition. We are able to artificially tune circuits with subgroup size distributions that are a better fit to the environment than the observed. This suggests that a combination of measurement error, constraint, and adaptive lag are diminishing the power of collective computation in this system. These results are relevant for a more general understanding of the emergence of ordered states in multi-scale social systems with adaptive properties–both natural and engineered.

Quantum Circuits with Classically Simulable Operator Scrambling.

We introduce a new family of quantum circuits for which the scrambling of a subspace of nonlocal operators is classically simulable. We call these circuits "super-Clifford circuits" since the Heisenberg time evolution of these operators corresponds to Clifford evolution in operator space. Thus we are able to classically simulate the time evolution of certain single Pauli strings into operators with operator entanglement that grows linearly with the number of qubits. These circuits provide a new technique for studying scrambling in systems with a large number of qubits, and are an explicit counter example to the intuition that classical simulability implies the absence of scrambling.

A model for self‐assembling circuits with voltage‐controlled growth

SummaryThe circuit tile assembly model (cTAM) consists of a voltage source and resistive circuit tiles, configured as a voltage divider, that attach to form resistive ladders or grids if the voltage on the boundary is greater than or equal to a threshold. The model produces a family of circuits whose composition and properties change with time. As growth proceeds, the voltage decreases until it no longer exceeds a threshold, which causes growth to cease. This is referred to as self‐controlled growth, because the properties of the assembly itself are the primary determinant in controlling the extent of the assembly. The model augments tile assembly models, which are programmable through specific chemical interactions, with an alternative electrical mechanism. The ladder and grid assemblies have bounded size and unique shape that are determined by parameters from the electrical network. Using the harmonicity of the electric potential, the shape of the grid assembly is shown to be symmetric around the main diagonal. Finally, two models of growth, differentiated by whether the voltage is measured before or after attachment, are equivalent. The model and analysis have potential application to self‐assembly of nanostructures, as well as to networks whose structure changes over time.

How many qubits are needed for quantum computational supremacy?

Quantum computational supremacy arguments, which describe a way for a quantum computer to perform a task that cannot also be done by a classical computer, typically require some sort of computational assumption related to the limitations of classical computation. One common assumption is that the polynomial hierarchy (PH) does not collapse, a stronger version of the statement thatP≠NP, which leads to the conclusion that any classical simulation of certain families of quantum circuits requires time scaling worse than any polynomial in the size of the circuits. However, the asymptotic nature of this conclusion prevents us from calculating exactly how many qubits these quantum circuits must have for their classical simulation to be intractable on modern classical supercomputers. We refine these quantum computational supremacy arguments and perform such a calculation by imposing fine-grained versions of the non-collapse conjecture. Our first two conjectures poly3-NSETH(a) and per-int-NSETH(b) take specific classical counting problems related to the number of zeros of a degree-3 polynomial innvariables overF2or the permanent of ann×ninteger-valued matrix, and assert that any non-deterministic algorithm that solves them requires2cntime steps, wherec∈{a,b}. A third conjecture poly3-ave-SBSETH(a′) asserts a similar statement about average-case algorithms living in the exponential-time version of the complexity classSBP. We analyze evidence for these conjectures and argue that they are plausible whena=1/2,b=0.999anda′=1/2.Imposing poly3-NSETH(1/2) and per-int-NSETH(0.999), and assuming that the runtime of a hypothetical quantum circuit simulation algorithm would scale linearly with the number of gates/constraints/optical elements, we conclude that Instantaneous Quantum Polynomial-Time (IQP) circuits with 208 qubits and 500 gates, Quantum Approximate Optimization Algorithm (QAOA) circuits with 420 qubits and 500 constraints and boson sampling circuits (i.e. linear optical networks) with 98 photons and 500 optical elements are large enough for the task of producing samples from their output distributions up to constant multiplicative error to be intractable on current technology. Imposing poly3-ave-SBSETH(1/2), we additionally rule out simulations with constant additive error for IQP and QAOA circuits of the same size. Without the assumption of linearly increasing simulation time, we can make analogous statements for circuits with slightly fewer qubits but requiring104to107gates.

Circuit Stability to Perturbations Reveals Hidden Variability in the Balance of Intrinsic and Synaptic Conductances.

Neurons and circuits each with a distinct balance of intrinsic and synaptic conductances can generate similar behavior but sometimes respond very differently to perturbation. Examining a large family of circuit models with non-identical neurons and synapses underlying rhythmic behavior, we analyzed the circuits' response to modifications in single and multiple intrinsic conductances in the individual neurons. To summarize these changes over the entire range of perturbed parameters, we quantified circuit output by defining a global stability measure. Using this measure, we identified specific subsets of conductances that when perturbed generate similar behavior in diverse individuals of the population. Our unbiased clustering analysis enabled us to quantify circuit stability when simultaneously perturbing multiple conductances as a nonlinear combination of single conductance perturbations. This revealed surprising conductance combinations that can predict the response to specific perturbations, even when the remaining intrinsic and synaptic conductances are unknown. Therefore, our approach can expose hidden variability in the balance of intrinsic and synaptic conductances of the same neurons across different versions of the same circuit solely from the circuit response to perturbations. Developed for a specific family of model circuits, our quantitative approach to characterizing high-dimensional degenerate systems provides a conceptual and analytic framework to guide future theoretical and experimental studies on degeneracy and robustness.SIGNIFICANCE STATEMENT Neural circuits can generate nearly identical behavior despite neuronal and synaptic parameters varying several-fold between individual instantiations. Yet, when these parameters are perturbed through channel deletions and mutations or environmental disturbances, seemingly identical circuits can respond very differently. What distinguishes inconsequential perturbations that barely alter circuit behavior from disruptive perturbations that drastically disturb circuit output remains unclear. Focusing on a family of rhythmic circuits, we propose a computational approach to reveal hidden variability in the intrinsic and synaptic conductances in seemingly identical circuits based solely on circuit output to different perturbations. We uncover specific conductance combinations that work similarly to maintain stability and predict the effect of changing multiple conductances simultaneously, which often results from neuromodulation or injury.

A comprehensive analysis on the resilience of adiabatic logic families against transient faults

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of digital systems. Nevertheless, their impact on the reliability of digital circuits due to susceptibility to soft errors has not been explored comprehensively. In this paper, we first try to survey some existing adiabatic logic families. Then we attempt to evaluate their reliability by validating their functionality under the effect of soft errors. Our evaluations which were conducted on a set of SPICE simulations have shown that amongst SCRL, 2LAL, RERL, PFAL, 2N2N2P and ECRL families the ECRL family is able to tolerate more than 90% of the injected transient faults and the applications with a high demand of reliability can use this family of adiabatic circuits. Furthermore, we will propose some suggestions for establishing reliable computations through adiabatic circuits.

Global dynamics of Chua Corsage Memristor circuit family: fixed-point loci, Hopf bifurcation, and coexisting dynamic attractors

This paper presents an in-depth and rigorous mathematical analysis of a family of nonlinear dynamical circuits whose only nonlinear component is a Chua Corsage Memristor (CCM) characterized by an explicit seven-segment piecewise-linear equation. When connected across an external circuit powered by a DC battery, or a sinusoidal voltage source, the resulting circuits are shown to exhibit four asymptotically stable equilibrium points, a unique stable limit cycle spawn from a supercritical Hopf bifurcation along with three static attractors, four coexisting dynamic attractors of an associated non-autonomous nonlinear differential equation, and four corresponding coexistingpinched hysteresis loops. Thebasin of attractions of the above static and dynamic attractors is derived numerically via global nonlinear analysis. When driven by a battery, the resulting CCM circuit exhibits a contiguous fixed-point loci, along with its DC V–I curve described analytically by two explicit parametric equations. We also proved the fundamental feature of theedge of chaos property; namely, it is possible to destabilize a stable circuit (i.e., without oscillation) and make it oscillate, by merely adding a passive circuit element, namely $$L >0$$. The CCM circuit family is one of the few known example of a strongly nonlinear dynamical system that is endowed with numerous coexisting static and dynamic attractors that can be studied both experimentally, and mathematically, via exact formulas.

Flag fault-tolerant error correction, measurement, and quantum computation for cyclic Calderbank-Shor-Steane codes

Flag qubits have recently been proposed in syndrome extraction circuits to detect high-weight errors arising from fewer faults. The use of flag qubits allows the construction of fault-tolerant protocols with the fewest number of ancillas known to-date. In this work, we prove some critical properties of CSS codes constructed from classical cyclic codes that enable the construction of a flag fault-tolerant error correction scheme. We then develop fault-tolerant protocols as well as a family of circuits for flag fault-tolerant error correction and operator measurement, requiring only four ancilla qubits and applicable to cyclic CSS codes of distance 3. The measurement protocol can be further used for logical Clifford gate implementation via quantum gate teleportation. We also provide examples of cyclic CSS codes with large encoding rates.

Bifurcation analyses and hardware experiments for bursting dynamics in non-autonomous memristive FitzHugh-Nagumo circuit

In this paper, a non-autonomous memristive FitzHugh-Nagumo (FHN) circuit is constructed using a second-order memristive diode bridge with LC network. For convenience of circuit implementation, an AC voltage source is adopted to substitute the original AC current stimulus. Stimulated by the slowly varying AC voltage source, the number, locations and stabilities of the equilibrium points slowly evolve with the time, which are thus indicated as the AC equilibrium points. Different sequences of fold and/or Hopf bifurcations are encountered in a full period of time series evolutions, leading to various kinds of chaotic or periodic bursting activities. To figure out the related bifurcation mechanisms, the fold and Hopf bifurcation sets are mathematically formulated to locate the critical bifurcation points. On this basis, the transitions between the resting and repetitive spiking states are clearly illustrated by the time series of the AC equilibrium points and state variables, from which Hopf/subHopf, Hopf/Hopf, and Hopf/fold bursting oscillations are identified in the specified parameter regions. Finally, based on a fabricated hardware circuit, the experimental measurements are executed. The results verify that the presented memristive FHN circuit indeed exhibits complex bursting activities, which enriches the family of memristor-based FHN circuits with bursting dynamics.

Fault-Tolerant Resource Estimation of Quantum Random-Access Memories

Quantum random-access look-up of a string of classical bits is a necessary ingredient in several important quantum algorithms. In some cases, the cost of such quantum random-access memory (qRAM) is the limiting factor in the implementation of the algorithm. In this paper we study the cost of fault-tolerantly implementing a qRAM. We construct and analyze generic families of circuits that function as a qRAM, discuss opportunities for qubit-time tradeoffs, and estimate their resource costs when embedded in a surface code.

Achieving Multi-Hop PRE via Branching Program

Proxy re-encryption ( $\mathsf {PRE}$ PRE ) is a fundamental cryptographic primitive in secure data sharing and e-mail forwarding, etc. To our knowledge, most existing efficient lattice-based $\mathsf {PRE}$ PRE schemes focus on the construction of single-hop, key-private, multi-bit and chosen-ciphertext attack ( $\text{CCA}$ CCA ), etc. Few works of literature discussed the detailed multi-hop construction over lattices. Very recently, Chandran et al. (PKC'14) proposed a lattice-based $\mathsf {PRE}$ PRE scheme that builds upon the key switching mechanism of Brakerski (CRYPTO'12), and pointed out that their scheme can achieve multi-hop $\mathsf {PRE}$ PRE scheme by the ideal circuit family for a directed graph $G$ G . In this paper, we are still working along this line and achieving multi-hop $\mathsf {PRE}$ PRE via the branching program ( $\mathsf {BP}$ BP ), which is one type of NC1 circuit and can be used to compute encrypted data. To our knowledge, we proposed the first multi-hop $\mathsf {PRE}$ PRE scheme via $\mathsf {BP}$ BP which supports homomorphic evaluation. We also analyze the security of our scheme under decisional learning with errors ( $\mathsf {LWE}$ LWE ) assumption.

Coat Circuits for DC–DC Converters to Improve Voltage Conversion Ratio

The voltage conversion ratio of basic dc/dc converters is limited due to the influence of parasitic elements of circuits and components. In this article, a family of passive circuits termed as “coat circuits” are proposed for conventional dc/dc converters. Not only voltage step-up capacity can be improved but also the voltage stress of components can be decreased by adding coat circuits to basic dc/dc converters. Moreover, no additional active switches are needed in the coat circuits, that means the control and driver circuits of the converters are not changed. The Cuk converter with the coat circuit has been analyzed as an example, and a 200 W experimental prototype has been built to verify the validity of the theoretical analysis.

Quasi-period, periodic bursting and bifurcations in memristor-based FitzHugh-Nagumo circuit

A third-order non-autonomous memristor-based FitzHugh-Nagumo (FHN) circuit is proposed through introducing a memristor emulator to realize the nonlinear function of the membrane voltage in the FHN model. This memristive FHN model possesses two slow time-scales, i.e. the external forcing current and the memristor inner state variable, and quasi-periodic, periodic bursting, and periodic behaviors are numerically revealed. The mechanism of the two-slow-time-scale-dependent periodic bursting dynamics is explored through using graphical method. Moreover, with the evolution of time, the equilibrium point of the memristive FHN circuit evolves between no equilibrium and line equilibrium point, and the stabilities of the line equilibrium point are highly related to the memristor initial condition. Consequently, the exhibited dynamics can be adjusted not only by tuning the system parameters, i.e. the forcing amplitude and frequency, but also by changing the memristor initial condition. The coexistence of multiple bifurcation modes are also found in some system parameter regions. Finally, a simulated circuit model is designed and PSIM circuit simulations are performed to confirm the numerical simulations. The presented memristive FHN circuit can enrich the family of memristor-based FHN circuits and their exhibited firing dynamics.