Failure Mechanism Of Interconnects Research Articles

Grain boundaries-dominated migration failure of copper interconnect under multiphysics field: Insight from theoretical modeling and finite element analysis

As the feature size of Cu interconnects in microelectronic devices are miniaturized into micro- and even nano-scale, the effects of grain boundaries (GBs) on the electromigration (EM) failure become more and more obvious. It is of fundamentally importance to investigate the grain boundaries dominated failure mechanism and lifetime of Cu interconnects. In this work, the interconnection models containing different grain boundaries were constructed by using finite element simulations. The simulation results indicate that the current density at Cu grain boundaries is lower, but the current will be increased locally, when it is almost perpendicular to grain boundaries. However, the temperature is higher locally at grain boundaries. In the early stage of atomic diffusion, thermal migration and stress migration also occur near grain boundaries, resulting in significant atomic segregation near grain boundaries, particularly at the intersection of grain boundaries and near the inclined grain boundaries with small angles to the current direction. The atomic diffusion is considerably accelerated as the density of grain boundaries is increased, but is slowed down by poorly connected columnar grain boundaries.

Study of the Interconnect Failure Mechanism and Micro-effort for ULSI

Study of the Interconnect Failure Mechanism and Micro-effort for ULSI

Metal nanofibrils embedded in long free-standing carbon nanotube fibers with a high critical current density

With the growth of nanoelectronics, the importance of thermal management in device packaging and the improvement of high-current-carrying interconnects/wires for avoiding the premature failure of devices have been emphasized. The heat and electrical transport properties of the bulk may not be valid in the characterization of a material at the nanometer level, because the phenomena that occur at the interfaces and grain boundaries become dominant. The failure mechanism of bulk metal interconnects has been understood in the context of electromigration; however, in nanoscale materials, the effect of the heat dissipation that occurs at the nanointerfaces may play an important role. Here, we report the preparation of continuous carbon nanotube (CNT)–Cu composite fibers that possess Cu nanofibrillar structures with a high current-carrying capacity. Various-shaped CNT–Cu microfibers with different Cu grain morphologies were produced via Cu electroplating on continuous CNT fibers. Cu fibril structures were embedded in the voids inside the CNT fiber during the early stage of electrodeposition. The temperature-dependent and magnetic field-dependent electrical properties and the ampacity of the produced CNT–Cu microfibers were measured, and the failure mechanism of the fiber was discussed. The interconnection of Cu nanograins on the surface of the individual CNTs contributed to the enhancement in the charge-carrying ability of the fiber. The effective ampacity of the Cu nanofibrils was estimated to be ~1 × 107 A/cm2, which is approximately 50 times larger than the ampacity measured for a bulk Cu microwire.

Surface diffusion induced shape evolution of multiple circular voids under high current density

To understand better the failure mechanism of interconnects under high current density, surface diffusion induced multi-voids shape evolution is investigated. The electric current field is solved analytically for a plate containing two circular voids. Based on the mass diffusion theory, the electromigration induced multi-voids shape evolution is predicted. For the isolated void case, the shape is generally preserved and moves steadily in the conductor. For the multi-voids case, a theoretical model is developed to describe the general behavior of voids shape evolution. It is noted that the steady shape of the initial circular void is broken, and bifurcation could occur due to asymmetry of the current distribution around the voids surface. By considering the multi-voids interaction effect, how the void collapses to a crack, coalesces with each other, or splits into smaller voids is clarified.

Electromigration Reliability of Passivated Gold Interconnects for GaAs Devices

The electromigration lifetimes of a very large quantity of passivated electroplated Au interconnects were measured utilizing high resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided large Joule-heated temperature gradients and electrical overstress failures. A maximum Joule-heated Au film temperature of 12°C was determined from measured temperature coefficients of resistance (TCRs). All Au interconnect lifetime distributions followed log-normal statistics. An activation energy of 0.80 ± 0.05 eV was measured from constant-current electromigration tests at multiple temperatures. A current density exponent of 1.91 ± 0.03 was extracted from multiple current densities at a single constant temperature. These electromigration model parameters correlate with the observed Au interconnect failure mechanism.

Interconnect Reliability Characterization of a High-Density 3-D Chip-on-Chip Interconnect Technology

This paper investigates the solder interconnect reliability of a high-density 3-D chip-on-chip technology under an accelerated thermal cycling (ATC) test condition through finite element (FE) modeling and experimental validation. The fabrication of the 3-D chip-on-chip technology is accomplished with a two-step gap control bonding process to minimize the solder squeezing phenomenon. The alternative goal of this paper is placed on the influences of underfill on the interconnect failure mechanism and reliability. With the calculated plastic strain, the thermal fatigue life of the most critical solder interconnect can be estimated through an empirical Coffin-Manson fatigue life prediction model. The effectiveness of the proposed FE modeling is demonstrated through ATC tests. Finally, to identify the parameters most affecting the lead-free solder interconnect reliability, both parametric FE analysis and a simulation-based experimental design scheme based on a response surface methodology are carried out with the validated FE model. Both the numerical and experimental results that underfill can not only change the interconnect failure mechanism from an interfacial crack between the Al pad and the copper (Cu) layer of the under bump metallurgy to a cohesive solder failure, but also greatly improve the solder interconnect thermal fatigue life by as much as 2.5 times. Furthermore, the experimental design demonstrates that both the Young's modulus of intermetallic compound and thermal expansion coefficient of underfill are identified as the parameters most affecting the solder interconnect reliability of the 3-D chip-on-chip technology.

Applications of finite element methods for reliability study of ULSI interconnections

Three main failure mechanisms of ULSI interconnects are the electromigration (EM), stress induced voiding (SIV) and low-k dielectric breakdown. Reliability tests for these mechanisms are too long to meet the development time requirement, and the underlying dominant mechanisms cannot be identified, rendering difficulty in design-in reliability for integrated circuit. Facing the challenges in the reliability study of the interconnect system, physics based simulation and modeling is found to be essential, and finite element method (FEM) is a suitable tool. A few examples on the application of FEM to study the degradation processes and identification of potential failure sites in interconnects due to EM and SIV are given here. The study of the process induced degradation of the effective k value of low-k dielectric in ULSI interconnect system using FEM is also presented.

Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

Integrated circuit (IC) manufacturing process reliability is gaining increasing importance in fabrication technology with decreasing device size and the impact of interconnect failure mechanisms. As device geometries are reduced, understanding and minimizing the sources of process-induced defects is critical to achieving process reliability and maintaining high device yields. It has been known that pattern missing and defects could be prevented by optimizing the process module tuning. The abnormal pattern collapse observed in this process and numerous defects could be prevented by optimizing the fabrication process module tuning. To successfully integrate submicron dual damascene process with good electrical and reliability performance after process improvement of lithography patterning, etching feasibility studies on semiconductor wafer fabrication processes were included. To suppress problems in the hard mask approach of photolithography and optimal etching patterning processes, the balance of the processes integration are quantitatively controlled with this optimum wafer integrated fabrication technologies.

Nondestructive Sensing of Interconnect Failure Mechanisms Using Time-Domain Reflectometry

This paper presents time-domain reflectometry (TDR) as a nondestructive sensing method for interconnect failure mechanisms. Two competing interconnect failure mechanisms of electronics were considered: solder joint cracking and solder pad cratering. A simple theoretical analysis is presented to explain the effect of each failure mechanism on the TDR reflection coefficient. Mechanical fatigue tests have been conducted to confirm the theoretical analysis. The test results consistently demonstrated that the TDR reflection coefficient gradually decreased as the solder pad separated from the circuit board, whereas it increased during solder joint cracking. Traditional test methods based on electrical resistance monitoring cannot distinguish between failure mechanisms and do not detect degradation until an open circuit has been created. In contrast, the TDR reflection coefficient can be used as a sensing method for the determination of interconnect failure mechanisms as well as for early detection of the degradation associated with those mechanisms.

The effects of encapsulation on deformation behavior and failure mechanisms of stretchable interconnects

In this paper, the effect of encapsulation on deformation behavior and failure mechanisms of stretchable interconnects is presented. Extensive numerical modeling is conducted for mechanical analysis of which the results are correlated with in-situ experimental observations. The numerical results reveal that by adding an encapsulation layer of various thickness (from 0.0 to 0.5 mm) on top of the stretchable interconnect, the out-of-plane deformation and in-plane geometrical opening are reduced. Consequently, not only the plastic strain in the metal increases but also the in-plane shear stress at the interconnect/substrate interface. In-situ electromechanical experiments combined with scanning electron micrographs and optical images confirm the numerical analysis. More specifically, it is found that two failure mechanisms are involved during the stretching process: interfacial delamination in a S-shape alongside the metal conductor and metal breakdown at the crests of the metal conductor. The encapsulated stretchable interconnect shows both failure mechanisms at a lower percentage elongation than the non-encapsulated stretchable interconnect. Even so, the onset point of interfacial delamination for the encapsulated stretchable interconnect occurs only at an impressive number of 63% elongation and metal rupture only at 120%. The in-plane shear strain contour, obtained by numerical simulation, agrees well with the delamination failure location observed in the experiment.

Failure of Flip-Chip Circuit Interconnects under High Current Density

Both Al interconnects and flip-chip solder bumps were sensitive to high current. The failure mechanism of circuits interconnects would be more complicated if the current density in circuits was exceed the critical magnitudes of electromigration in both Al interconnects and solder bumps. The failure of circuit interconnects under different magnitudes of current density was studied and the interaction of electromigration in solder bumps and Al interconnects was discussed. The circuit interconnects of flip chip show three failure phenomena under high current density: voids in Al final metal, inter-diffusion of Al and SnPb, and melting of solder bumps. The voids in Al metal show the directional diffusion of Al atoms was mainly controlled by the electron wind fore. However the inter-diffusion of Al and SnPb demonstrated the electron wind force to Sn and Pb atoms would be ignored in contrast with chemical potential gradient or intrinsic stress. The flow of Sn and Pb atoms under high current density was in opposite direction with electron wind force and uniform with chemical potential gradient.

Circuit level interconnect reliability study using 3D circuit model

Integrated circuit (IC) reliability is gaining increasing concerns in IC technology with decreasing device size, and the impact of interconnect failure mechanisms on IC failure rate increases significantly with decreasing interconnect dimension and increasing number of interconnect levels. In this work, we attempt a first step in the study of interconnect electromigration reliability in integrated circuit using a complete 3D circuit model. 3D circuit model is necessary because all integrated circuits are 3D in their actual physical implementation, and 3D model is essential for the study of today interconnect reliability. As temperature and stress distributions in the interconnect are crucial to its reliability, we demonstrate our method through the computation of their distributions in a simple inverter circuit under typical normal operating condition, and the locations of the electromigration weak spots in the interconnect system are identified.

Electromigration effect on pancake type void propagation near the interface of bulk solder and intermetallic compound

Due to the reduction in the size of electronic devices and solder interconnects, their current densities are rapidly increasing and the effect of electromigration becomes more critical to interconnect failure. Traditional methods are not sufficient to determine the failure mechanisms of solder interconnects under such high current densities. An approach to predict the electromigration effect upon interconnect failure including void propagation is timely and useful to the electronics industry. The stress gradient in a 95.5Sn-4Ag-0.5Cu eutectic solder with a void defect is analyzed numerically to determine the electromigration and stress migration forces. A kinetic mass diffusion model is developed to predict void width and propagation speed near the interface between the intermetallic compound and bulk solder caused by electromigration. A three-dimensional finite element analysis has been performed to analyze the current crowding effect in the interconnect. The proposed kinetic model gives a reasonable prediction for the void width and propagation velocity as compared with experimental results.

Interfacial Fracture Analysis of CMOS Cu/Low-$k$ BEOL Interconnect in Advanced Packaging Structures

The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.

Failure mechanisms of legacy aircraft wiring and interconnects

This paper presents a comprehensive list of the causes and modes of failure and ageing in legacy aircraft wiring and interconnects. Taxonomies of the electrical, mechanical, chemical and thermal stresses that contribute to the various stages of ageing and/or failure are presented. A failure modes effects and analysis (FMEA) is conducted to categorize the most serious failures. The order of severity in the FMEA is backed up by maintenance data gathered by the Royal Air Force (RAF) base Brize Norton during routine inspection.

Stress Evolution Related to Metal Routing in Submicron Multilevel Interconnects: Void and Extrusion

Failure mechanism of submicron multilevel interconnects encapsulated in a quad flat package subjected to high temperature operating life (HTOL) test under temperature and bias has been investigated. With the presence of void formation in the upper metal, Al extrudes from the lower metal to the adjacent metal lines leading to a fatal short failure. Void itself is not critical but later the growth of extrusion compromises the integrity and circuit reliability. Such a failure mechanism is explained with stress evolution on the metal routing associated with tensile stress imposed on the upper metal adhered to a thicker interlayer dielectric on certain points then relived with void formation that triggers compressive stress on the lower metal layer causing Al extrusion. For the purpose of verification, a new layout of the metal routing is committed and subjected to the HTOL. We found that the aspect ratio of the metal line significantly influences the integrity of submicron multilevel interconnects.

Copper Hillock Induced Copper Diffusion and Corrosion Behavior in a Dual Damascene Process

A copper hillock induced interconnect failure mechanism is presented. The copper hillock is frequently generated during a copper dual damascene process and hillock formation is found to degrade the interconnect integrity by affecting the following process steps. The copper hillock appears to damage the capping layer and results in copper corrosion during via etch. The corrosion generates copper particles inside via holes and the defects are found to make the following metal depositions incomplete during via formation. Based on the observations, a copper hillock induced defect model is proposed and a new copper process is suggested to reduce copper hillocks.

The Effect of Immersion Sn coating on the Electromigration Failure Mechanism and Lifetimes of Cu Dual Damascene Interconnects

AbstractIn sub-micron dual damascene Cu interconnects, electromigration occurs mainly along the interfaces between Cu and dielectric cap layer. Many reports have shown that the interface of Cu/dielectric cap is the dominant diffusion path. In-situ electromigration experiments were carried out recently by A. V. Vairagar etal [APPL. PHYS. LETT., 85, 2502 (2004)] to investigate the electromigration failure mechanisms in the upper and lower layers in dualdamascene Cu test structures. It was found that electromigration-induced void first nucleates at locations which are far from the cathode, then moves along the Cu/dielectric cap interface in opposite direction of electron flow, and eventually causes void agglomeration at the via in the cathode end to open the interconnect. In the present study, immersion Sn (20 nm) was employed after CMP and before SiN deposition. All the samples, with a line-width of 0.28 um, were assessed by package level electromigration tests at 300°C under a current density of 3.6MA/cm2. We found that immersion Sn surface treatment effectively introduced the Cu-Sn bonding to the Cu/dielectric interface and has influenced electromigration along the Cu/dielectric interfaces. Failure analysis shows that the samples with these Sn processes have a median-time-to-failure almost 1 order of magnitude larger than the control samples. A careful characterization utilizing FIB and SEM cross-sectional images shows that the failure mechanism has changed due to the Sn surface treatments. After electromigration-induced void nucleation, its movement is blocked by the strong Cu-Sn bonding so that its growth is localized and occurs along grain boundaries. With the increased impedance to surface diffusion, failure analysis seems to indicate that grain boundary diffusion now participates in the void movement and growth, which is proposed to be the reason for the increased lifetime.

A stress-induced diffusion model for failure of interconnects in microelectronic devices

Voiding and open-circuit failures from cracking of interconnects in microelectronic devices are often observed during isothermal aging and thermal fatigue tests with or without electric current flow. Although the effects of many factors on the failure rate have been investigated experimentally, it is not yet known how to extrapolate the results of accelerated tests to normal operating conditions. Theoretical failure models for isothermal aging and thermal fatigue tests are constructed from diffusion theory and fracture mechanics in this paper. The results from many investigations can be incorporated into this model to explain many of the observed phenomena, for example, effects of the aging temperature, interconnect stress, linewidth, line thickness, passivation, interlayer dielectric stress, etc. Patterned Al-Cu interconnects were thermally cycled in air. It was found that the failure mechanisms of interconnects under isothermal aging and thermal fatigue are the same. Effects of hold time, frequency, and thermal fatigue temperatures on failure rate were studied both experimentally and theoretically. The predicted results according to the present failure model show excellent agreement with experiments.