Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

Abstract

Integrated circuit (IC) manufacturing process reliability is gaining increasing importance in fabrication technology with decreasing device size and the impact of interconnect failure mechanisms. As device geometries are reduced, understanding and minimizing the sources of process-induced defects is critical to achieving process reliability and maintaining high device yields. It has been known that pattern missing and defects could be prevented by optimizing the process module tuning. The abnormal pattern collapse observed in this process and numerous defects could be prevented by optimizing the fabrication process module tuning. To successfully integrate submicron dual damascene process with good electrical and reliability performance after process improvement of lithography patterning, etching feasibility studies on semiconductor wafer fabrication processes were included. To suppress problems in the hard mask approach of photolithography and optimal etching patterning processes, the balance of the processes integration are quantitatively controlled with this optimum wafer integrated fabrication technologies.