Interconnect Reliability Characterization of a High-Density 3-D Chip-on-Chip Interconnect Technology

Abstract

This paper investigates the solder interconnect reliability of a high-density 3-D chip-on-chip technology under an accelerated thermal cycling (ATC) test condition through finite element (FE) modeling and experimental validation. The fabrication of the 3-D chip-on-chip technology is accomplished with a two-step gap control bonding process to minimize the solder squeezing phenomenon. The alternative goal of this paper is placed on the influences of underfill on the interconnect failure mechanism and reliability. With the calculated plastic strain, the thermal fatigue life of the most critical solder interconnect can be estimated through an empirical Coffin-Manson fatigue life prediction model. The effectiveness of the proposed FE modeling is demonstrated through ATC tests. Finally, to identify the parameters most affecting the lead-free solder interconnect reliability, both parametric FE analysis and a simulation-based experimental design scheme based on a response surface methodology are carried out with the validated FE model. Both the numerical and experimental results that underfill can not only change the interconnect failure mechanism from an interfacial crack between the Al pad and the copper (Cu) layer of the under bump metallurgy to a cohesive solder failure, but also greatly improve the solder interconnect thermal fatigue life by as much as 2.5 times. Furthermore, the experimental design demonstrates that both the Young's modulus of intermetallic compound and thermal expansion coefficient of underfill are identified as the parameters most affecting the solder interconnect reliability of the 3-D chip-on-chip technology.