Fabrication Of Graphene Devices Research Articles

In Situ Growth of Graphene Catalyzed by a Phase-Change Material at 400°C for Wafer-Scale Optoelectronic Device Application.

The use of metal foil catalysts in the chemical vapor deposition of graphene films makes graphene transfer an ineluctable part of graphene device fabrication, which greatly limits industrialization. Here, an oxide phase-change material (V2 O5 ) is found to have the same catalytic effect on graphene growth as conventional metals. A uniform large-area graphene film can be obtained on a 10nm V2 O5 film. Density functional theory is used to quantitatively analyze the catalytic effect of V2 O5 . Due to the high resistance property of V2 O5 at room temperature, the obtained graphene can be directly used in devices with V2 O5 as an intercalation layer. A wafer-scale graphene-V2 O5 -Si (GVS) Schottky photodetector array is successfully fabricated. When illuminated by a 792nm laser, the responsivity of the photodetector can reach 266 mA W-1 at 0 V bias and 420 mAW-1 at 2 V. The transfer-free device fabrication process enables high feasibility for industrialization.

Transfer-Free CVD Growth of High-Quality Wafer-Scale Graphene at 300 °C for Device Mass Fabrication.

Direct chemical vapor deposition of graphene on semiconductors and insulators provides high feasibility for integration of graphene devices and semiconductor electronics. However, the current methods typically rely on high temperatures (>1000 °C), which can damage the substrates. Here, a growth method for high-quality large-area graphene at 300 °C is introduced. A multizone furnace with gradient temperature control was designed according to a computational fluid dynamics model. The crucial roles of the chamber pressure in the film continuity and hydrogen composition in the graphene defect density at low temperature were revealed. As a result, a uniform graphene film with the Raman ratio ID/IG = 0.08 was obtained. Furthermore, a technique of laminating single-crystal Cu foil as a sacrificial layer on the substrate was proposed to realize transfer-free growth, and a wafer-scale graphene transistor array was demonstrated with good performance consistency, which paves the way for mass fabrication of graphene devices.

Making monolayer graphene photoluminescent by electron-beam-activated fluorination approach

The past one and half decades have witnessed a tremendous development of graphene electronics, and the key to the success of graphene is its exceptional properties. The lacking of an inherent bandgap endows graphene with excellent electrical properties but considerably limits its applications in light-emitting and high-performance graphene-based devices. Herein, an approach for the direct writing of semiconducting and photoluminescent fluorinated graphene (C4F) patterns on monolayer graphene by an optimized electron-beam-activated fluorination technique is reported. A series of characterization approaches, such as atomic force microscopy, X-ray photoelectron spectroscopy and Raman spectroscopy were used to demonstrate the successful preparation of C4F for maskless lithography. Specially, a sharp and strong photoluminescence located at the purple light range of ∼380 nm was observed in C4F, demonstrating a desirable semiconducting nature, and the bandgap was further confirmed by follow-up electrical measurements, where the C4F filed-effect transistor exhibited a p-type semiconductor behavior and significantly enhanced on/off ratio. Therefore, this work provides a novel technique for the fabrication of graphene devices for promising electronic and optoelectronic applications, but also opens a route towards the tailoring and engineering of electronic properties of graphene.

Evolution of the Raman 2D’ mode in monolayer graphene during electrochemical doping

Effective charge doping and control of the Fermi level shift is a crucial aspect in graphene device fabrication. Raman spectroscopy is extensively used for primary characterization of such samples, however, quantification of carrier concentration using the known G-2D vector analysis can pose problems when more sources of phonon renormalization are present, for example lattice deformation or disorder. In such cases, analysis of another Raman mode can provide the needed missing information. In this study, chemical vapor-deposition-grown single-layer graphene was monitored by in-situ Raman spectroelectrochemistry with the focus on the behavior of the 2D’ mode upon the application of electrochemical potential. We analyzed the changes of the Raman peak intensity, frequency and linewidth of the 2D’ mode as a function of electrode potential in detail and compared the obtained results with well-known behavior of the G and 2D modes during electrochemical doping.

Graphene-Based Flexible Electrode for Electrocardiogram Signal Monitoring

With the rapidly aging society and increased concern for personal cardiovascular health, novel, flexible electrodes suitable for electrocardiogram (ECG) signal monitoring are in demand. Based on the excellent electrical and mechanical properties of graphene and the rapid development of graphene device fabrication technologies, graphene-based ECG electrodes have recently attracted much attention, and many flexible graphene electrodes with excellent performance have been developed. To understand the current research progress of graphene-based ECG electrodes and help researchers clarify current development conditions and directions, we systematically review the recent advances in graphene-based flexible ECG electrodes. Graphene electrodes are classified as bionic, fabric-based, biodegradable, laser-induced/scribed, modified-graphene, sponge-like, invasive, etc., based on their design concept, structural characteristics, preparation methods, and material properties. Moreover, some categories are further divided into dry or wet electrodes. Then, their performance, including electrode–skin impedance, signal-to-noise ratio, skin compatibility, and stability, is analyzed. Finally, we discuss possible development directions of graphene ECG electrodes and share our views.

Effect of different types of substrate surface treatments on the graphene device performance

Graphene–substrate interface is very crucial for analyzing graphene device performance. In this article, we have shown how the graphene device performance got affected because of different types of substrate surface treatment techniques used before graphene transfer. For fabrication of graphene devices, monolayer chemical vapor deposition (CVD) graphene was transferred onto SiO2 grown thermally on Si substrate. Forming gas annealed SiO2/Si shows better device performance as compared with as‐grown SiO2 on Si substrate. A further effect of oxygen plasma and argon plasma cleaning of SiO2 surface before graphene transfer was investigated. Forming gas annealing improves the performance and plasma treatment degrade the graphene devices' performance.

Nanofabrication of graphene field-effect transistors by thermal scanning probe lithography

The development of a scalable and cost-effective nanofabrication method is of key importance for future advances in nanoelectronics. Thermal scanning probe lithography (t-SPL) is a growing nanopatterning method with potential for parallelization, offering unique capabilities that make it an attractive candidate for industrial nanomanufacturing. Here, we demonstrate the possibility to apply t-SPL for the fabrication of graphene devices. In particular, we use t-SPL to produce high performing graphene-based field effect transistors (FETs). The here described t-SPL process includes the fabrication of high-quality metal contacts, as well as patterning and etching of graphene to define the active region of the device. The electrical measurements on the t-SPL fabricated FETs indicate a symmetric conductance at the Dirac point and a low specific contact resistance without the use of any contact engineering strategy. The entire t-SPL nanofabrication process is performed without the need for masks, and in ambient conditions. Furthermore, thanks to the t-SPL in situ simultaneous patterning and imaging capability, no markers are required. These features substantially decrease fabrication time and cost.

(Invited) Challenges of Graphene Process Integration in CMOS Technology

Compatibility of graphene device fabrication process with Si integrated circuit (IC) manufacturing platforms can enhance the implementation of graphene in electronic and optoelectronic applications and their commercialization. Recent demonstrations of hybrid graphene-Si devices on a wafer scale [1, 2] clearly indicate increasing maturity of the graphene technology. However, there are remaining questions about the manufacturability, as well as the integration and compatibility with Si technology which are seen as prerequisites to the commercialization of graphene (opto-) electronic devices [3, 4]. Despite the remarkable progress in recent years, protocols used for the fabrication of graphene devices often lack the required stability and compatibility which in turn hinders access to the large-scale semiconductor device manufacturing infrastructure. From this point of view, it is of utmost importance to investigate preparation of graphene devices in conditions resembling as close as possible to the Si-based IC production environment. Although this approach may pose inherent risks to the fabrication toolsets, it provides a rare opportunity to explore the engineering aspects of graphene device preparation in a relevant production environment. In this paper we focus on engineering aspects of graphene device fabrication under constraints of manufacturability. We demonstrate some of the key stepping stones which can form a pathway to the fabrication of graphene-based components using tools and processes applied in the IC manufacturing in a 200 mm wafer Si technology environment. As a case study, we present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200 mm wafer pilot line routinely used for the fabrication of ICs in 0.13/0.25um SiGe BiCMOS (bipolar-complementary metal-oxide-semiconductor) technologies. Following the presentation of key process steps and selected electrical characterization results, we point out to the challenges and roadblocks which need to be overcome to enable integration of this material with Si devices. Although Cu substrates offer graphene an outstanding quality, layer transfer from Cu is associated with a significant risk of metallic contaminations which pose limitations on handling of graphene in CMOS processing lines. For this reason, our experiments rely on graphene grown on Ge surfaces which has been proven to be front-end-of-line compatible in terms of purity. Chip-size patches of graphene are transferred from the epi-Ge/Si growth wafer by electrochemical delamination to various sorts of patterned 200 mm wafers on which the further process development takes place. This method of graphene transfer is not yet fully compatible with the Si technology; however, it offers convenient prototyping opportunities as an intermediate solution until full 200mm wafer transfer processes as for example the wafer bonding is developed. Encapsulation of deposited graphene is essential to protect its properties from the environment and the destructive influences of subsequent processing. The key element of the encapsulation in our fabrication scheme is a thin (20 nm-50 nm) SiN layer deposited by low power plasma-enhanced chemical vapor deposition (PECVD). It has been demonstrated that layers of SiN can be grown by PECVD directly on the graphene with excellent uniformity and electrical performance while preserving its crystalline quality and transport properties. The added value of PECVD technique is that it is widely used in the Si IC manufacturing. We adapted this approach to form closed and smooth (rq = 0.47 nm) encapsulating layers of SiN (refractive index n = 2.02 at l = 633 nm) directly on transferred graphene. The second element of the encapsulation is realized by the deposition of a SiO2 layer on the SiN film by using CVD. References Y.-M. Lin, A. Valdes-Garcia, S.-J. Han, D.B. Farmer, I. Meric, Y. Sun, Y. Wu, C. Dimitrakopoulos, A. Grill, P. Avouris, K.A. Jenkins, Science, 332, 1294 (2011)S. Goossens, G. Navickaite, C. Monasterio, S. Gupta, J.J. Piqueras, R. Perez, G. Burwell, I. Nikitskiy, T. Lasanta, T. Galan, E. Puma, A. Centeno, A. Pesquera, A. Zurutuza, G. Konstantatos, F. Koppens, NaturePhotonics, 11, 366 (2017) S. Park, Nature Reviews Materials, 1, 16085 (2016)G. Ruhl, S. Wittmann, M. Koenig, D. Neumaier, Beilstein J. Nanotechnol., 8, 1056 (2017)

(Invited) Challenges of Graphene Process Integration in CMOS Technology

In this paper we have investigated various steps of graphene device fabrication in a 200 mm wafer Si technology environment. This work has also introduced some of the key process modules which may pave the way to large-scale manufacturing of hybrid graphene-Si components. Although the demonstrated process flow requires further improvements to increase device yield and reduce variability the practical relevance is emphasized by the facts that first the proposed processes and materials enable efficient encapsulation and low-resistance metal-graphene contacts and secondly they are compatible with those used in the large-scale fabrication of Si-based ICs. Among the key factors which are limiting the performance and yield of the graphene are uniformity after transfer, process-related contaminations, and poor adhesion/delamination of graphene during various processing steps. In fact, availability of clean and uniform graphene layers on large diameter wafers (200/300 mm) can be considered as a critical prerequisite to further progress in the process integration of graphene devices in Si technology environment.

High-Quality Magnetotransport in Graphene Using the Edge-Free Corbino Geometry.

We report fabrication of graphene devices in a Corbino geometry consisting of concentric circular electrodes with no physical edge connecting the inner and outer electrodes. High device mobility is realized using boron nitride encapsulation together with a dual-graphite gate structure. Bulk conductance measurement in the quantum Hall effect (QHE) regime outperforms previously reported Hall bar measurements, with improved resolution observed for both the integer and fractional QHE states. We identify apparent phase transitions in the fractional sequence in both the lowest and first excited Landau levels (LLs) and observe features consistent with electron solid phases in higher LLs.

Wafer Scale Graphene Field Effect Transistors on Thin Thermal Oxide

Graphene, an allotrope of carbon, shows ambipolar transfer characteristics with a linear dispersion relation where the conduction and valence band meets at the Dirac point 1. Owing to an absence of bandgap, it is not feasible to use graphene in logic applications though it is possible to use graphene in analog and RF circuits2. Significant efforts towards the growth and transfer of graphene onto arbitrary substrates 3 4 , 5 6 has made it feasible to scale up graphene device fabrication – early focus on single, exfoliated devices has given way to large area, many-device wafers. From a practical standpoint, a lower operating voltage range, minimal unintentional doping of graphene during processing, and excellent device stability at room temperature is required. Most of the earlier graphene based devices were fabricated on thick (90nm or higher) thermal SiO2 substrate as they provide a better optical contrast after transferring graphene. Unfortunately, this attributes to a higher operating voltage in order to modulate the graphene device. In this work, we demonstrate the feasibility of making devices on thin, 10 nm thermal SiO­2 gate dielectric using CVD graphene with minimal shift in the Dirac point and excellent stability during subsequent operation cycles in air at room temperature. The 10nm thermal SiO2 has a breakdown field of ~9.7MV/cm and mobilities as high as 2200 cm2/V·S is achieved in a relatively small operating voltage (±8V). A higher mobility is typically seen for devices located at the center of the transferred graphene region. The 10nm dielectric used in our process is challenging for integration since graphene cannot be visually inspected during device fabrication, but we have overcome this limitation by implementing specialized characterization steps that allow us to monitor the graphene. A lower contact resistivity of 500 Ω-µm and sheet resistance (RSh) of 400Ω/□ is observed at a higher doping level achieved by applying a fixed back gate bias with Ni/Au contact. A similar trend is seen in the RSh extracted from a more appropriate test structure (Van der Pauw), wherein there is a minimal metal contact overlap with graphene. The hysteresis for these graphene devices are consistently less than or equal to 0.3V within the ± 8V sweeping voltage range. Therefore, we demonstrate the fabrication of wafer scale graphene devices with excellent process control on thin dielectric substrate with minimal doping and trapped charge. This could pave way for realization of high performance, low power consuming nanoelectronics with graphene. (1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Zhang, Y.; Dubonos, S. V.; Grigorieva, I. V.; Firsov, A. A. Electric Field Effect in Atomically Thin Carbon Films. Science. 2004, 306, 666–669. (2) Schwierz, F. Graphene Transistors. Nat. Nano. 2010, 5, 487–496. (3) Colombo, L.; Wallace, R. M.; Ruoff, R. S. Graphene Growth and Device Integration. Proc. IEEE 2013, 101, 1536–1556. (4) Banszerus, L.; Schmitz, M.; Engels, S.; Dauber, J.; Oellers, M.; Haupt, F.; Watanabe, K.; Taniguchi, T.; Beschoten, B.; Stampfer, C. Ultrahigh-Mobility Graphene Devices from Chemical Vapor Deposition on Reusable Copper. Sci. Adv. 2015, 1, e1500222(1-6). (5) Kim, H. H.; Lee, S. K.; Lee, S. G.; Lee, E.; Cho, K. Wetting-Assisted Crack- and Wrinkle-Free Transfer of Wafer-Scale Graphene onto Arbitrary Substrates over a Wide Range of Surface Energies. Adv. Funct. Mater. 2016,26, 2070-2077. (6) Li, X.; Cai, W.; An, J.; Kim, S.; Nah, J.; Yang, D.; Piner, R.; Velamakanni, A.; Jung, I.; Tutuc, E.; Banerjee,S. K;Colombo, L.; Ruoff. R. S . Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science . 2009, 324, 1312–1314.

Transfer-free growth of graphene on Al2O3 (0001) using a three-step method

The transfer process before graphene device fabrication could worsen the performance of graphene device greatly, so a transfer-free growth method for preparing graphene films is demanded urgently. Herein, we propose a novel three-step method to achieve transfer-free graphene films on Al2O3 (0001) substrates. Cu (111) films and carbon source were co-deposited on α-Al2O3 (0001) substrates by metal-organic chemical vapor deposition (MOCVD) at one step, then graphene was synthesis by a rapid annealing process, transforming the carbon source in copper into graphene films. Finally, a transfer-free graphene film with an ultra-smooth surface (∼3.49 nm) is achieved by etching the copper film on Al2O3(0001). Crystallographic characterization demonstrated the as-deposited Cu films show a nature of epitaxial single crystal, with a smooth surface (∼6.89 nm). Few layer graphene films (3–4 layers) with least defect concentration were grown at annealing time of 20 min.

Growth of monolayer graphene on nanoscale copper-nickel alloy thin films

Growth of high quality, monolayer graphene on copper thin films on silicon wafers is a promising approach to large-scale, direct graphene device fabrication. However, the presence of potential dewetting issues in the copper film during graphene growth has historically limited this method of device fabrication. This paper shows that the use of a nickel adhesion layer coupled with the copper film helps to mitigate the dewetting problem and produce uniform monolayer graphene growth over 97% coverage on films. The feasibility of monolayer graphene growth on Cu-Ni alloy films as thin as 150 nm in total is demonstrated. During the graphene growth on Cu-Ni films, the nickel adhesion layer uniformly diffuses into the copper thin film resulting in a Cu-Ni alloy, helping to promote graphene nucleation and large area surface coverage. Furthermore, it was found that the use of extremely thin metal catalyst films also constraint the total amount of carbon that can be absorbed into the film during growth, which helps to eliminate adlayer formation and promote monolayer growth regardless of alloying content, thus improving the monolayer fraction of graphene coverage on the thinner films. These results suggest a path forward for the large scale integration of high quality, monolayer graphene into nanoelectronic and nanomechanical devices.

(Invited) Graphene Synthesis and Processing on Ge Substrates

Graphene is considered as a material which can enable new functionalities and performance improvements in a large variety of applications, among them in microelectronics [1, 2]. In microelectronics, techniques required for commercial large scale fabrication of graphene devices are not yet in place and further progress towards wafer-scale processing is required. Development of a wafer-scale Si technology-compatible graphene synthesis method and a toolbox of processes dedicated to handling, cleaning, patterning as well as integration of graphene with semiconductors, insulators, and metals is viewed as a prerequisite to practical applications of this material in electronic and photonic devices [3]. Semiconducting Ge surfaces appeared recently as attractive substrates for chemical vapor deposition (CVD) of graphene. There are several advantages of using them instead of metals. Firstly, the risk of metallic contaminations [4] is eliminated, ensuring the front-end-of-line compatibility in the device manufacturing process. Secondly, the thermal expansion coefficient mismatch between the Ge substrate and graphene is significantly lower than in the Cu-graphene system. This provides an opportunity to reduce the density of wrinkles which originate from thermal stress release and cause scattering of charge carriers in graphene. Furthermore, as a result of very low carbon solubility in Ge, the graphene growth on Ge can proceed, similarly to Cu substrates, in a “self-limiting” manner enabling more straightforward process control than for example on Ni. Finally, synthesis on patterned semiconducting Ge may enable direct use of graphene in some device concepts without the need of transfer which is inevitable in case of metallic substrates. In this talk, we will review the recent progress in graphene synthesis on Ge achieved by IHP and our collaborators starting from proof-of-concept molecular beam growth experiments [5], through low- [6] and high-pressure [7] CVD on Ge single crystals and Ge epi-layers on Si, to 200 mm wafer-scale CVD synthesis on Ge(100)/Si(100) virtual substrates. As an optimization approach towards improved rotational alignment of graphene on Ge [8,9] we will present results from the preparation of Ge(110)/Si(110) wafers and graphene growth on them. Beyond growth we will look at selected aspects of subsequent processing in a 200 mm Si wafer pilot line including patterning and interaction with photoresists as well as the deposition of other materials on graphene. Among the challenges ahead, re-usability of the Ge virtual substrates and wafer-scale graphene transfer procedures eliminating disadvantages of currently existing noble metal-assisted techniques [8] will be addressed. [1] A.C. Ferrari et al., “Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems”, Nanoscale, 2015, 7, 4598-4810 [2] G. Fiori et al., “Electronics based on two-dimensional materials”, Nature Nanotechnology 2014, 9, 768–779 [3] L. Colombo et al., “Graphene growth and device integration”, IEEE Proceedings, 2013, 101, 1536-1556 [4] G. Lupina et al., “Residual metallic contamination of transferred chemical vapor deposited graphene”, ACS Nano, 2015, 9, 4776-4785 [5] G. Lippert et al., “Graphene grown on Ge(001) from atomic source”, Carbon, 2014, 75, 104-112 [6] J. Dabrowski et al., “Direct growth of low-doped graphene on Ge/Si(100) surfaces”, 2016, arXiv:1604.02315 [7] I. Pasternak et al., “Graphene growth on Ge(100)/Si(100) substrates by CVD method”, Scientific Reports, 2016, 6, 21773 [8] J.-H. Lee et al., “Wafer scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium”, Science, 2014, 344, 286-289 [9] B. Kiraly et al., “Electronic and mechanical properties of graphene-germanium interfaces grown by chemical vapor deposition”, Nano Lett., 2015, 15, 7414-7420

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.

Graphene processing using electron beam assisted metal deposition and masked chemical vapor deposition growth

The fabrication of graphene devices can be challenging due to exposure to harsh chemicals and mechanical wear such as ultrasonication used for cleaning in photolithography and metal deposition. Common graphene processing methods often damage fragile graphene sheets and can ruin the device during fabrication. The authors report a facile method to overcome many of these challenges, which is specifically compatible with graphene grown by chemical vapor deposition (CVD). Using e-beam assisted metal deposition to deposit fine platinum features, electrodes can be deposited directly on graphene while still on the copper foil used as the catalyst during the CVD growth. The graphene and electrodes are then transferred to an insulating substrate, without further processing. This method preserves the graphene/metal interface from exposure to harsh chemicals used in traditional lithography methods, and avoids many of the conventional processing steps, which can cause unwanted doping, and damage or destroy the graphene. The authors observe an increase in Raman D-mode in the graphene under the Pt deposit, which suggests that the deposition method facilitates chemisorption by slightly abrading the surface of graphene surface during deposition. Using e-beam assisted electrode deposition in conjunction with masked CVD graphene growth on copper, the authors show the feasibility of fabricating complete graphene devices without subjecting the graphene to lithography, plasma etching, metal lift-off steps, or even shadow mask processing.

ChemInform Abstract: Spintronics with Graphene Quantum Dots

AbstractReview: 159 refs.

Spintronics with graphene quantum dots

magnified imageThanks to its intrinsic ability to preserve spin coherence, graphene is a prime material for spintronics. In this review article, we summarize recent achievements related to spintronics in graphene quantum dots and motivate this field from a spintronics and a materials science point of view. We focus on theory but also discuss recent experiments. The main sources of spin decoherence are interactions with lattice excitations and the hyperfine interaction with present nuclear spins. We explain effective spin–phonon coupling in detail and present a generic power law for the spin relaxation time T1 as a function of the magnetic field. For specific cases, we discuss spin relaxation in detail. The Heisenberg exchange interaction is paramount for coherent spin qubit operation and addressed in the context of magnetism in graphene nanoflakes. Nuclear spins in the host and surrounding material can be considered by several means and the influence of 13C nuclei has been studied in detail. Impressive advances in general spintronics and the fabrication of graphene devices are likely to spark significant advances in spintronics with graphene quantum dots in the near future. magnified image(© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)

Large scale integration of graphene transistors for potential applications in the back end of the line

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2V−1s−1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Microstructure fabrication process induced modulations in CVD graphene

The systematic Raman spectroscopic study of a “mimicked” graphene device fabrication is presented. Upon photoresist baking, compressive stress is induced in the graphene which disappears after it is removed. The indirect irradiation from the electron beam (through the photoresist) does not significantly alter graphene characteristic Raman peaks indicating that graphene quality is preserved upon the exposure. The 2D peak shifts and the intensity ratio of 2D and G band, I(2D)/I(G), decreases upon direct metal deposition (Co and Py) suggesting that the electronic modulation occurs due to sp2 C-C bond weakening. In contrast, a thin metal oxide film deposited graphene does not show either the significant 2D and G peaks shift or I(2D)/I(G) decrease upon the metal deposition suggesting the oxide protect the graphene quality in the fabrication process.