(Invited) Graphene Synthesis and Processing on Ge Substrates

Abstract

Graphene is considered as a material which can enable new functionalities and performance improvements in a large variety of applications, among them in microelectronics [1, 2]. In microelectronics, techniques required for commercial large scale fabrication of graphene devices are not yet in place and further progress towards wafer-scale processing is required. Development of a wafer-scale Si technology-compatible graphene synthesis method and a toolbox of processes dedicated to handling, cleaning, patterning as well as integration of graphene with semiconductors, insulators, and metals is viewed as a prerequisite to practical applications of this material in electronic and photonic devices [3]. Semiconducting Ge surfaces appeared recently as attractive substrates for chemical vapor deposition (CVD) of graphene. There are several advantages of using them instead of metals. Firstly, the risk of metallic contaminations [4] is eliminated, ensuring the front-end-of-line compatibility in the device manufacturing process. Secondly, the thermal expansion coefficient mismatch between the Ge substrate and graphene is significantly lower than in the Cu-graphene system. This provides an opportunity to reduce the density of wrinkles which originate from thermal stress release and cause scattering of charge carriers in graphene. Furthermore, as a result of very low carbon solubility in Ge, the graphene growth on Ge can proceed, similarly to Cu substrates, in a “self-limiting” manner enabling more straightforward process control than for example on Ni. Finally, synthesis on patterned semiconducting Ge may enable direct use of graphene in some device concepts without the need of transfer which is inevitable in case of metallic substrates. In this talk, we will review the recent progress in graphene synthesis on Ge achieved by IHP and our collaborators starting from proof-of-concept molecular beam growth experiments [5], through low- [6] and high-pressure [7] CVD on Ge single crystals and Ge epi-layers on Si, to 200 mm wafer-scale CVD synthesis on Ge(100)/Si(100) virtual substrates. As an optimization approach towards improved rotational alignment of graphene on Ge [8,9] we will present results from the preparation of Ge(110)/Si(110) wafers and graphene growth on them. Beyond growth we will look at selected aspects of subsequent processing in a 200 mm Si wafer pilot line including patterning and interaction with photoresists as well as the deposition of other materials on graphene. Among the challenges ahead, re-usability of the Ge virtual substrates and wafer-scale graphene transfer procedures eliminating disadvantages of currently existing noble metal-assisted techniques [8] will be addressed. [1] A.C. Ferrari et al., “Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems”, Nanoscale, 2015, 7, 4598-4810 [2] G. Fiori et al., “Electronics based on two-dimensional materials”, Nature Nanotechnology 2014, 9, 768–779 [3] L. Colombo et al., “Graphene growth and device integration”, IEEE Proceedings, 2013, 101, 1536-1556 [4] G. Lupina et al., “Residual metallic contamination of transferred chemical vapor deposited graphene”, ACS Nano, 2015, 9, 4776-4785 [5] G. Lippert et al., “Graphene grown on Ge(001) from atomic source”, Carbon, 2014, 75, 104-112 [6] J. Dabrowski et al., “Direct growth of low-doped graphene on Ge/Si(100) surfaces”, 2016, arXiv:1604.02315 [7] I. Pasternak et al., “Graphene growth on Ge(100)/Si(100) substrates by CVD method”, Scientific Reports, 2016, 6, 21773 [8] J.-H. Lee et al., “Wafer scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium”, Science, 2014, 344, 286-289 [9] B. Kiraly et al., “Electronic and mechanical properties of graphene-germanium interfaces grown by chemical vapor deposition”, Nano Lett., 2015, 15, 7414-7420