Fabrication Of Field-effect Transistors Research Articles

A Single-Crystal Antimony Trioxide Dielectric for 2D Field-Effect Transistors.

The remarkable potential of two-dimensional (2D) materials in sustaining Moore's law has sparked a research frenzy. Extensive efforts have been made in the research of utilizing 2D semiconductors as channel materials in field-effect transistors. However, the next generation of integrated devices requires the integration of gate dielectrics with wider bandgaps and higher dielectric constants. Here, insulating α-Sb2O3 single-crystal nanosheets are synthesized by one-step chemical vapor deposition method. Importantly, the α-Sb2O3 single-crystal dielectric exhibits a high dielectric constant of 11.8 and a wide bandgap of 3.78 eV. Besides, the atomically smooth interface between α-Sb2O3 and MoS2 enables the fabrication of dual-gated field-effect transistors with the top gate dielectric of α-Sb2O3 nanosheets. The field-effect transistors exhibit a switching ratio of exceeding 108, which achieves the manipulation of field-effect transistors by using 2D dielectric materials. These results hold significant implications for optimizing the performances of 2D devices and innovating microelectronics.

Demonstration of aluminum nitride metal oxide semiconductor field effect transistor on sapphire substrate

Abstract Aluminum nitride (AlN) is a promising ultrawide bandgap material with significant advantages for power electronics and optoelectronic applications due to its high breakdown voltage, mobility, and thermal conductivity. AlN Schottky barrier diodes (SBDs) and metal semiconductor field effect transistors (MESFETs) have shown potential but are limited by issues such as high off-state leakage current and complex structures to achieve ohmic contacts. To address these challenges, we report on the fabrication and characterization of an AlN metal oxide semiconductor field effect transistor (MOSFET) with a recessed gate structure. The source and drain contacts were fabricated on n-doped AlN epitaxy using Ti-based contacts with a Ti/Al/Ti/Au metal stack. To evaluate the performance of these contacts, a circular transmission line model (CTLM) was employed, and contacts were annealed at various temperatures ranging from 750 to 950 °C in a nitrogen ambient. Our results reveal that unannealed Ti-based contacts on AlN showed no current conduction. However, annealing these contacts at 950 °C for 30 s significantly reduced the specific contact resistance to 0.148 Ω·cm2, achieving an ~80% reduction compared to samples annealed at 750 °C. Utilizing these optimized contact conditions, we fabricated, to the best of our knowledge, the first AlN MOSFET. The fabricated AlN MOSFET exhibits a threshold voltage of −10.91 V, an effective mobility of 2.95 cm2/Vs, an on-off current ratio spanning two orders of magnitude, and a reverse breakdown voltage of approximately ~250 V in air without a field plate. 

Process Development of a Liquid-Gated Graphene Field-Effect Transistor Gas Sensor for Applications in Smart Agriculture

A compact, multi-channel ionic liquid-gated graphene field-effect transistor (FET) has been proposed and developed in our work for on-field continuous monitoring of nitrate nitrogen and other nitrogen fertilizers to achieve sustainable and efficient farming practices in agriculture. However, fabricating graphene FETs with easy filling of ionic liquids, minimal graphene defects, and high process yields remains challenging, given the sensitivity of these devices to processing conditions and environmental factors. In this work, two approaches for the fabrication of our graphene FETs were presented, evaluated, and compared for high yields and easy filling of ionic liquids. The process difficulties, major obstacles, and improvements are discussed herein in detail. Both devices, those fabricated using a 3 μm-thick CYTOP® layer for position restriction and volume control of the ionic liquid and those using a ~20 nm-thick photosensitive hydrophobic layer for the same purpose, exhibited typical FET characteristics and were applicable to various application environments. The research findings and experiences presented in this paper will provide important references to related societies for the design, fabrication, and application of liquid-gated graphene FETs.

Conjugated Polymer-Based Photo-Crosslinker for Efficient Photo-Patterning of Polymer Semiconductors.

Photo-patterning of polymer semiconductors using photo-crosslinkers has shown potential for organic circuit fabrication via solution processing techniques. However, the performance of patterning, including resolution (R), UV light exposure dose, sensitivity (S), and contrast (γ), remains unsatisfactory. In this study, a novel conjugated polymer based photo-crosslinker (PN3, Figure 1a) is reported for the first time, which entails phenyl-substituted azide groups in its side chains. Due to the potential π-π interactions between the conjugated backbone of PN3 and those of polymer semiconductors, PN3 exhibits superior miscibility with polymer semiconductors compared to the commonly used small molecule photo-crosslinker 4Bx (Figure 1a). Consequently, photo-patterning of polymer semiconductors with PN3 demonstrates improved performance with much lower UV light exposure dose, higher S and higher γ compared to 4Bx. By utilizing electron beam lithography, patterned arrays of polymer semiconductors with resolutions down to 500nm and clearer edges are successfully fabricated using PN3. Furthermore, patterned arrays of PDPP4T, the p-type semiconductor (Figure 1b), after being doped, can function as source-drain electrodes for fabricating field-effect transistors (FETs) with comparable charge mobility and significantly lower sub-threshold swing value compared to those with gold electrodes.

Fabrication of graphene field effect transistors on complex non-planar surfaces

Graphene field effect transistors (GFETs) are promising devices for biochemical sensing. Integrating GFETs onto complex non-planar surfaces could uncap their potential in emerging areas of wearable electronics, such as smart contact lenses and microneedle sensing. However, the fabrication of GFETs on non-planar surfaces is challenging using conventional lithography approaches. Here, we develop a combined spray-coating and photolithography setup for the scalable fabrication of GFETs on non-planar surfaces and demonstrate their application as integrated GFETs on microneedles. We optimize the setup to pattern ∼ 67 μm long GFET channels across the microneedle tips. Graphene is deposited between photo-patterned electrodes by spray-coating a liquid-phase exfoliated graphene ink while monitoring the channel resistance to achieve the required conductivity. The formation of the GFET channels is confirmed by SEM and EDX mapping, and the GFETs are shown to modulate in solution. This demonstrates an approach for manufacturing graphene electronic devices on complex non-planar surfaces like microneedles and opens possibilities for wearable GFET microneedle sensors for real-time monitoring of biomarkers.

Transfer-free p-type graphene field-effect transistors with high mobility and on/off ratio

Graphene is considered a promising material because of the novel functionalities associated with its outstanding charge transport properties. However, because graphene has no bandgap, its electrical conductivity cannot be controlled as in semiconductors, at present. Although many attempts have been made to achieve a bandgap opening in graphene, a meaningful bandgap opening for p-type field-effect-transistors (FETs) still remains a challenge. In this study, boron-doping in transfer-free monolayer graphene was successfully demonstrated for digital logic devices. Our approach is highly versatile, as it allows the fabrication of p-type single-crystal graphene FETs having a mobility of ∼290 cm2V−1s−1, an on/off ratio of 1.9 × 105, and a subthreshold swing of 70 mVdec−1. The scalability and versatility of this transfer-free approach for the fabrication of p-type graphene FETs pave the way for high-performance p-type graphene-based digital logic circuits.

Full Two-Dimensional Ambipolar Field-Effect Transistors for Transparent and Flexible Electronics.

The unique features of two-dimensional (2D) materials provide significant opportunities for the development of transparent and flexible electronics. Recently, ambipolar 2D semiconductors have advanced innovative applications such as CMOS-like circuits, reconfigurable circuits, and ultrafast neuromorphic image sensors. Here, we report on the fabrication of full 2D ambipolar field-effect transistors (FETs), in which graphene serves as the source/drain/gate electrodes, WSe2 is for the channel, and h-BN is for the dielectric. The produced ambipolar FETs exhibit comparable on-currents in the n-branch and p-branch with on/off ratios up to 108. By using two ambipolar FETs in series, a CMOS-like inverter is demonstrated with a maximum gain of up to 147, which can work in both the first and third quadrants by controlling the supply voltages and input voltages. The full 2D ambipolar FETs yield a transmittance of over 70% for visible light on transparent glass and achieve a curvature radius of less than 0.5 cm for bending on polyethylene terephthalate (PET) substrate. The work is helpful for the application of ambipolar 2D materials-based devices in transparent and flexible electronics.

Synthesis and Characterization of Epitaxially-Fused Quantum Dot Superlattices at the Single Grain Limit

Epitaxially-fused superlattices of colloidal quantum dots (QD epi-SLs) may exhibit electronic minibands and high-mobility charge transport, but doing so requires epi-SLs with extremely high degrees of spatial and chemical (compositional) uniformity. In this talk, I will discuss both our efforts to understand and improve the epi-SL formation process, as well as recent charge transport studies on single epi-SL grains.Epi-SLs are synthesized from a parent SL structure, typically composed of QDs with long insulating ligands. Over the past several years, we have developed insight into the physical and chemical mechanisms by which this parent SL structure is converted into an epi-SL. I will present detailed, multi-model structural characterization of the SL structures, which unveils the astonishing choreographic process by which millions of QDs rotate and translate, in concert, to form the epi-SL.This structural transformation is initiated by chemical changes to the QD ligand layer, usually through manual introduction of liquids into the SL film. Mechanistic studies into this ligand-exchange process reveal a multi-step chemical sequence that initiates with a simple acid-base reaction. We exploit this insight to fabricate epi-SLs by means of photochemical triggering (using ultraviolet illumination) rather than alternative “hands-on” techniques which suffer from poor experimental control and pronounced chemical inhomogeneity and structural damage in the films. The use of light to trigger the SL conversion process enables much finer control in both the temporal and spatial domains, opening the door to much larger-area SL films and direct photopatterning of epi-SLs.In the latter portion of the talk, I will present recent work charge transport studies in individual, highly-ordered PbSe QD epi-SL grains. One technical challenge in making these devices is the inherent mismatch in using traditional microfabrication techniques to make single-grained devices of air-sensitive materials. Here, we demonstrate the air-free fabrication of microscale field-effect transistors (μ-FETs) with channels consisting of single PbSe QD epi-SL grains (~ 1 -10 µm grain sizes) and analyze charge transport phenomena in these samples. The devices exhibit p-channel or ambipolar transport with a hole mobility as high as 3.5 cm2 V–1 s–1 at 290 K and 6.5 cm2 V–1 s–1 at 170–220 K, one order of magnitude larger than that of previous QD solids.

High‐Precision Materials Printer for Fast Prototyping of Electronic Devices Based on 2D Materials

AbstractThere is an increasing interest in printed electronics driven principally by flexible and wearable applications. The interest stems from the ability to fabricate electronic devices, such as Field Effect Transistors (FET), more efficiently in terms of materials use and cost‐effectively than traditional lithographic techniques. Challenges persist in achieving high resolution and accuracy in defining device geometry. In the study, a high‐resolution materials printer able to achieve resolutions in the micron range, surpassing the capabilities of commercially available printers is successfully designed and fabricated. The printer incorporates an all‐in‐one printing system, comprising Inkjet and a Dip Pen Nanolithography (DPN) technique, enabling both additive and subtractive manufacturing at the microscale. The experiments demonstrate the successful fabrication of FETs based on 2D materials (2DMs), with micrometric channel lengths exhibiting a high degree of controllability and repeatability, even when contacting limited channel regions as micrometer‐sized molybdenum disulfide (MoS2) flakes. Electrical characterizations of the fabricated devices underscore the significant technological advancements achieved by the prototypes.

Band alignment and charge transfer mechanisms in the prediction of advanced gate dielectrics for carbon nanotube field-effect transistors

The search for novel gate dielectrics to mitigate interface state density is a pressing concern in the fabrication of high-performance carbon nanotube field-effect transistors (CNT-FETs). In this study, we investigated the feasibility of employing strontium titanate (STO) with an ultra-high dielectric constant as the gate dielectric in CNT-FETs. By combining X-ray photoelectron spectroscopy measurements with first-principles calculations, we determined the band offsets between CNT and STO, as well as between CNT and conventional gate dielectrics such as HfO2 and SiO2. The valence/conduction band offset (VBO/CBO) at the STO/CNT interface is found to be 1.1 eV/1.5 eV, which is the smallest among all studied interfaces, followed by those at HfO2/CNT interface (VBO = 1.3 eV/CBO = 3.4 eV) and SiO2/CNT interface (VBO = 3.6 eV/CBO = 4.5 eV). Moreover, charge transfer at the STO/CNT interface exhibits two orders of magnitude lower values compared to that at HfO2/CNT interface and is also significantly smaller than that at SiO2/CNT interface. This phenomenon can be ascribed to the combined effects of van der Waals forces at the STO/CNT interface and fewer dangling bonds on the STO surface. These findings suggest exceptional compatibility between STO and CNT, making STO highly suitable for high-performance CNT-FETs.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Study of ISFET for KCl sensing

This work presents the fabrication and electrical characterization of the Ion Sensitive Field Effect Transistor (ISFET) exposed to potassium chloride (KCl) solutions. The focus of the study is to compare two measurements methods and verify the effects of these methods in the device threshold voltage (VTH) sensitivity to the different KCl concentrations. First, a reference electrode (a platinum needle) is placed in the sample solution over the gate area of the device, demonstrating that the threshold voltage decreases with the increase of the KCl concentration. The method shows a sensitivity of 10.44 mV/mM for the low KCl concentration range (0 to 10 mM) and 0.5 mV/mM for the higher KCl concentration range (10 to 100 mM). The second method involves inserting a second platinum electrode into the solution on the field oxide. This method proposes the KCl electrolysis to increase the selectivity for potassium ions. The result allows the next steps for potassium sensing biosensor application with selective membranes.

Quasi-Van der Waals Epitaxial Growth of γ'-GaSe Nanometer-Thick Films on GaAs(111)B Substrates.

GaSe is an important member of the post-transition-metal chalcogenide family and is an emerging two-dimensional (2D) semiconductor material. Because it is a van der Waals material, it can be fabricated into atomic-scale ultrathin films, making it suitable for the preparation of compact, heterostructure devices. In addition, GaSe possesses unusual optical and electronic properties, such as a shift from an indirect-bandgap single-layer film to a direct-bandgap bulk material, rare intrinsic p-type conduction, and nonlinear optical behaviors. These properties make GaSe an appealing candidate for the fabrication of field-effect transistors, photodetectors, and photovoltaics. However, the wafer-scale production of pure GaSe single-crystal thin films remains challenging. This study develops an approach for the direct growth of nanometer-thick GaSe films on GaAs substrates by using molecular beam epitaxy. It yields smooth thin GaSe films with a rare γ'-polymorph. We analyze the formation mechanism of γ'-GaSe using density-functional theory and speculate that it is stabilized by Ga vacancies since the formation enthalpy of γ'-GaSe tends to become lower than that of other polymorphs when the Ga vacancy concentration increases. Finally, we investigate the growth conditions of GaSe, providing valuable insights for exploring 2D/three-dimensional (3D) quasi-van der Waals epitaxial growth.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Realization of single MoTe2 crystal in-plane TFET by laser-induced doping technique

Significant recent progress has been achieved in the fabrication of tunnel field-effect transistors (TFETs) utilizing transition metal dichalcogenides (TMDCs) materials, particularly focusing on out-of-plane heterojunction structures. Due to the inherent limitations of doping technology for TMDCs, there have been limited investigations into the development of in-plane TFETs. In this study, we present the realization of an in-plane TFET based on a single crystal of multilayer MoTe2, utilizing a regioselective doping technique through laser irradiation. By constructing a p+/i/n++ homojunction structure, a band-to-band tunneling dominated performance with a minimum subthreshold swing value of 75 mV/dec and an on/off ratio of 105 was obtained at a low temperature. Furthermore, the “OFF” and “ON” state currents of the TFET operation were smaller than the gated diode operation in this structure, which is consistent with the tunneling mechanism.

Comprehensive Study and Design of Graphene Transistor.

Graphene, renowned for its exceptional electrical, optical, and mechanical properties, takes center stage in the realm of next-generation electronics. In this paper, we provide a thorough investigation into the comprehensive fabrication process of graphene field-effect transistors. Recognizing the pivotal role graphene quality plays in determining device performance, we explore many techniques and metrological methods to assess and ensure the superior quality of graphene layers. In addition, we delve into the intricate nuances of doping graphene and examine its effects on electronic properties. We uncover the transformative impact these dopants have on the charge carrier concentration, bandgap, and overall device performance. By amalgamating these critical facets of graphene field-effect transistors fabrication and analysis, this study offers a holistic understanding for researchers and engineers aiming to optimize the performance of graphene-based electronic devices.

Removal of conjugated polymer on carbon nanotube array by dry process

With the progress in the purity and alignment of semiconductor carbon nanotubes (CNTs), how to efficiently remove the conjugated polymers twining round CNTs has become an important and urgent matter for the further development of CNT electronics. The removal of conjugated polymers (CPs) by wet cleaning will inevitably lead to the destruction of the morphology of aligned CNT array films, which will cause the monolayered CNTs to form agglomeration or stacking. Therefore, it is necessary to develop a dry method to remove CPs on the aligned CNT films. In this work, we studied the thermal decomposition characteristics of CNTs and CPs in detail, and found that the ratio of the oxidative decomposition rate of CNTs and CPs could reach up to 35.7 in the oxygen environment at 450 °C. The transmission electron microscopes (TEMs) show that such a dry treatment process can effectively remove the polymer on CNTs without affecting the morphology of CNT arrays. The Raman spectrum show that ratio of G/D of the annealed sample is as high as 41.8, which indicates that the CNTs are not detectable damaged during the annealed process. The fabricated field-effect transistors (FETs) with a length of 2 μm exhibit a current on/off ratio higher than 104 and a current density higher than 660 μA/μm, which further justifies that the CNT arrays treated by the dry method exhibit high quality.

Effect of Thickness and Thermal Treatment on the Electrical Performance of 2D MoS2 Monolayer and Multilayer Field-Effect Transistors

We deposited high-quality molybdenum disulfide (MoS2) monolayer and multilayer crystals on SiO2/Si substrates, by means of a chemical vapor deposition (CVD) process at atmospheric pressure. Notably, NaCl salt was used as component of the precursors to assist the growth of MoS2 crystals, which were intended for use as the active channel layer in the fabrication of field-effect transistors (FETs). The resulting MoS2 crystals from this CVD process were analyzed by optical, scanning electron, and atomic force microscopies, and by Raman and photoluminescence spectroscopies. The optical images and the micrographs obtained by SEM revealed the formation of dispersed MoS2 crystals with a triangular shape all over the SiO2 surface. The thickness of the MoS2 crystals, analyzed by atomic force microscopy, showed minimum values of around 0.7 nm, confirming the formation of monolayers. Additionally, multilayers with larger thickness were also identified. The Raman and photoluminescence spectra of the MoS2 crystals corroborated the formation of single and multiple layers. The fabrication of the FET back-SiO2 -gate configuration was made by depositing patterned source and drain Ti contacts on the dispersed MoS2 crystals to achieve the Ti/MoS2/SiO2/Si layer stacks. MoS2-based FETs with one and three layers were assembled and their electrical response analyzed by I–V output and transfer curves showing the typical characteristics of an n-type semiconductor channel operating in depletion mode. The electrical performance parameters of the devices, such as mobility and threshold voltage, were also determined from this analysis. Finally, to enhance their electrical response, the MoS2-based devices were thermally annealed at 200 °C for 30 min in Ar atmosphere. The increase in the mobility of the device was 176% compared to the device before the treatment.

A negative photoconductivity photodetector based on two-dimensional Nb3Cl8.

Negative photoconductivity (NPC)-based photodetectors offer a new direction for energy-efficient photodetection technologies, featuring low energy consumption and high responsivity. Two-dimensional (2D) materials are particularly promising for implementing NPC due to their large surface area, abundant surface states, and tunable bandgap properties. In this context, 2D Nb3Cl8, with its unique kagome lattice structure and broad absorption spectrum, has attracted considerable interest. Notably, metal halides such as Nb3Cl8 demonstrate significant potential as NPC materials due to their low anionic and cationic bonding strength, which allows for the formation of vacancy defects with high probability. However, the NPC characteristics of Nb3Cl8 have not been thoroughly investigated. In this study, we fabricated field-effect transistors (FETs) using Nb3Cl8 single crystals synthesized via chemical vapor transport (CVT). These devices exhibited an electron mobility of 4.24 × 10-3 cm2 V-1 s-1 and a high Ion/Ioff ratio of 1.42 × 104. Notably, Nb3Cl8-based photodetectors demonstrated consistent NPC behavior across a wide wavelength range of 400-1050 nm, with a high responsivity of 156.82 mA W-1 at 400 nm. We propose that the trapping effect due to defect levels within the bandgap is the primary cause of this NPC phenomenon. The present findings reveal the unique photodetector properties of Nb3Cl8 and highlight its promise in energy-efficient photodetectors and various optoelectronic applications.

Analytical modelling and reliability analysis of charge plasma-assisted Mg2Si/Si heterojunction doping less DGTFET for low-power switching applications

Fabrication of tunnel field effect transistor (TFET) confronts various challenges, one of which is random dopant fluctuation (RDF), which diminishes the benefits associated with low subthreshold swing (SS) and high ION/IOFF ratio. By conducting physics-based 2D analytical modelling, this paper proposes a magnesium silicide/silicon (Mg2Si/Si) heterojunction-based doping less double gate tunnel field effect transistor (HB-DL-DGTFET). This work utilizes the concept of charge plasma to tackle the issues of RDF. The analytical analysis in this study is based upon the determination of the center-channel potential by solving 2D Poisson’s equation, considering appropriate boundary conditions. Here, surface potential, electric field, energy bands, drain current and threshold voltage are extracted mathematically. In addition to the aforementioned parameters, several other analog performance parameters like transconductance, drain conductance, device efficiency, intrinsic gain, output resistance and channel resistance have also been studied in this context. The analytical findings have been duly validated using the ATLAS TCAD device simulator. Furthermore, this work focuses on exploring proposed device reliability through an investigation of, the influence of interface trap charges (ITC), present at the Si/SiO2 interface. The study analyses ITC's impact on analog performance and the obtained results are compared with that of conventional doping less DGTFET (C-DL-DGTFET). The simulation results reveal that HB-DL-DGTFET exhibits greater immunity against ITC. Thus, validating the potential of HB-DL-DGTFET as a superior candidate for low-power switching applications.