Extracted Interface State Research Articles

(Invited, Digital Presentation) Interface Charge Trapping and Scattering in SiC MOSFET Channels

The channel conductivity of SiC MOSFETs is severely limited by charge trapping at interface states and mobility limiting scattering processes. In this talk, the status of interface state passivation for both n- and p-channel 4H-SiC MOSFETs will be presented. First, results from capacitance-based methods to extract interface state density (Dit) across the entire 4H-SiC band gap for thermally grown nitrided silicon dioxide gate dielectrics will be presented, emphasizing the critical importance of the SiO2(N)/SiC interface composition and nitrogen bonding. Next, the scattering mechanisms for channel electrons and holes in these devices will be analyzed and contrasted by Hall measurements. [1] The transport will be characterized as a function of temperature and substrate-bias within an effective transverse electric field model. The final part of the talk will focus on latest development on deposited dielectrics for 4H-SiC. Deposited dielectrics are an attractive alternative to thermal oxidation as it minimizes the release of carbon and the perturbation of surface crystal structure and opens the possibility of ‘high-k’ dielectrics with higher permittivity than SiO2. Herein, the key importance of 4H-SiC surface control prior to dielectric deposition will highlighted using results obtained for atomic layer deposition (ALD) of Aluminum Oxide (Al2O3) [2]. To this end, a systematic variation of SiC surface termination with processes involving oxygen, hydrogen and nitrogen will be presented. The composition of the deposited films and the interfacial bonding will be characterized for various deposition processes and correleated with electrical measurements . It will be demonstrated that surface nitridation followed by H2 annealing prior to ALD results in a factor of 2 higher channel mobility than typical NO annealed thermal SiO2. This is due to the formation of stable sub-nm SiON layers that passivates the surface and enables the formation of high-quality interfaces between SiC and deposited dielectric. In addition, the results indicate that clean Si-H terminated surfaces formed by hydrogen etching and annealing, prior to dielectric deposition leads to uniform nucleation of Al2O3. The reduction of Dit is also accompanied by improvements in oxide charge trapping and bias instability, but dielectric leakage current is significantly higher for Al2O3 compared to SiO2 due to bulk trap-assisted tunneling in Al2O3. The reliability is a significant challenge that need to be overcome to exploit the enhanced mobilities and make deposited dielectrics competitive with traditional nitrided SiO2.Acknowledgments: The authors acknowledge support from the US Army Research Laboratory (grant ARMY-W911NF-18-2-0160) and US Department of Energy (subcontracted to National Renewable Energy Laboratory, grant NREL-AHL-9-92632-01). The authors also acknowledge the support Dr. Leonard C. Feldman (Auburn, Rutgers) and Mr. Hengfei Gu (Rutgers) for help with XPS measurements. The authors also deeply thank Ms. T Isaacs-Smith, Ms. Lu Wang (Auburn), Dr. K. Ramadoss and Dr. D. Morisette (Purdue Univ.) for useful discussions and help with fabrication.[1] S. Das et al., J. Appl. Phys. 130, 225701, (2021).[2] I. U. Jayawardhena et al., J. Appl. Phys. 129, 75702, (2021) Figure 1

Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET

A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I- V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I- V modeling results: an universal mobility degradation normalization parameter N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it,ref</sub> = ~ 4.1 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I- V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress.

Structural, Chemical and Electrical Properties of Au/La2O3/n-GaN MIS Junction with a High-k Lanthanum Oxide Insulating Layer

This paper demonstrates the role of high-k La2O3 on the electrical performance of the Au/n-GaN Schottky junction (SJ) as an insulating layer between the Au and n-GaN films. First, the La2O3 is deposited on a n-type GaN surface by e-beam technique and analysed for its structural and chemical properties with x-ray diffraction (XRD) and x-ray photoelectron spectroscopy (XPS) approaches. XRD and XPS results confirmed the growth of La2O3 on the n-GaN surface. Then, the Au/La2O3/n-GaN metal/insulator/semiconductor (MIS) junction is fabricated and analysed for its electrical properties and compared with the SJ electrical results. The MIS junction exhibits a good rectifying nature with a low leakage current compared to the SJ. Experimental findings reveal a higher barrier height obtained for the MIS junction than the SJ, suggesting that the barrier height is altered by the La2O3 insulating layer. Also, the barrier heights are estimated by Cheung’s, Norde functions and ΨS–V plot, and the values are nearly matched with each other, indicating the techniques used here are valid. The extracted interface state density (NSS) of MIS junction is lower than the SJ, implying the La2O3 insulating layer plays a vital role in the decreased NSS. Experimental findings confirmed that the Schottky emission governs the reverse current in SJ. However, for the MIS junction, the Poole–Frenkel and Schottky emissions are the dominant current conduction mechanisms in the lower and higher bias regions.

Performance Enhancement for Charge Trapping Memory by Using Al2O3/HfO2/Al2O3 Tri-Layer High-κ Dielectrics and High Work Function Metal Gate

In this work, we have fabricated and systematically characterized a type of charge trapping memory (CTM) device with Al2O3/HfO2/Al2O3 tri-layer high-κ dielectric stacks and high work function tungsten metal gate (named as MAHAS in short). The extracted interface state density (Dit) value for the MAHAS memory is comparatively low owing to the optimized high-κ/Si interface quality using SiO2 ultrathin film (∼10 Å) grown by deionized water/O3. The MAHAS memory devices demonstrate desirable memory effects, especially significantly improved program and erase (P/E) speed. A large hysteresis memory window of 5.4 V by ± 10 V sweeping voltage and ∼2.7 V flat-band voltage shift by programming at +7 V for 100 μs are obtained. With respect to memory reliability, the MAHAS memory shows negligible memory window degradation after 106 P/E cycles, and the memory window retains 72.4% of the originally stored charge even after 105 s’ retention. With the simple structure and improved operation efficiency, the proposed MAHAS memory device is promising for future nonvolatile charge trapping memory applications.

Barrier Parameters and Current Transport Characteristics of Ti/p-InP Schottky Junction Modified Using Orange G (OG) Organic Interlayer

A Ti/Orange G/p-InP metal/interlayer/semiconductor (MIS) junction has been prepared with Orange G (OG) organic layer by electron beam evaporation and spin coating processes. The electrical properties of Ti/p-InP metal/semiconductor (MS) and Ti/OG/p-InP MIS junctions have been analyzed based on current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The MIS junction exhibited higher rectifying behavior than the MS junction. The higher barrier height (BH) of the MIS junction compared with the MS junction indicates effective modification by the OG layer. Also, the BH, ideality factor, shunt resistance, and series resistance were extracted based on the I–V characteristic, Cheung’s and Norde’s methods, and the ΨS–V plot. The BH evaluated by Cheung’s and Norde’s methods and the ΨS–V plot was shown to be similar, confirming the reliability and validity of the methods applied. The extracted interface state density (N SS) of the MIS junction was less than for the MS junction, revealing that the OG organic layer reduced the N SS value. Analysis demonstrated that, in the lower bias region, the reverse current conduction mechanism was dominated by Poole–Frenkel emission for both the MS and MIS junction. Meanwhile, in the higher bias region, Schottky emission governed the reverse current conduction mechanism. The results suggest that such OG layers have potential for use in high-quality electronic devices.

Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

Analysis of 4H-SiC MOS Capacitors on Macro-Stepped Surfaces

In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (&lt;1nm), surface with one with a roughness of ~40nm, characterized by big macrosteps and large terraces. We compared the two surfaces for different thermal oxide thicknesses, ranging from dOx = 3.6 nm to dOx = 32 nm. The extracted interface state traps (Dit) shows a small, but systematic, decrease of ~10-15 % for the samples with macrosteps.

Microstructural, electrical and frequency-dependent properties of Au/p-Cu2ZnSnS4/n-GaN heterojunction

An Au/Cu2ZnSnS4 (CZTS)/n-GaN heterojunction (HJ) is fabricated with a CZTS interlayer and probed its chemical states, structural, electrical and frequency-dependent characteristics by XPS, TEM, I-V and C-V measurements. XPS and TEM results confirmed that the CZTS films are formed on the n-GaN surface. The band gap of deposited CZTS film is found to be 1.55eV. The electrical properties of HJ correlated with the Au/n-GaN Schottky junction (SJ). The Au/CZTS/n-GaN HJ reveals a good rectification nature with high barrier height (0.82eV) compared to the Au/n-GaN SJ (0.69eV), which suggests the barrier height is influenced by the CZTS interlayer. The barrier height values assessed by I-V, Cheung’s and Norde functions are closely matched with one other, thus the methods used here are reliable and valid. The extracted interface state density (NSS) of Au/CZTS/n-GaN HJ is lower compared to the Au/n-GaN SJ that suggests the CZTS interlayer plays an important role in the reduction of NSS. Moreover, the capacitance-frequency (C-f) and conductance-frequency (G-f) characteristics of SJ and HJ are measured in the range of 1kHz–1MHz, and found that the capacitance and conductance strappingly dependent on frequency. It is found that the NSS estimated from C-f and G-f characteristics is lower compared to those estimated from I-V characteristics. Analysis confirmed that Poole-Frenkel emission dominates the reverse leakage current in both SJ and HJ, probably related to the structural defects and trap levels in the CZTS interlayer.

Effect of interface and bulk traps on the C–V characterization of a LPCVD-SiNx/AlGaN/GaN metal-insulator-semiconductor structure

Silicon nitride (SiNx) film grown by low-pressure chemical vapor deposition (LPCVD) is utilized as a gate dielectric for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Trap distribution at the gate-dielectric/III-nitrides interface is characterized by a temperature-dependent ac-capacitance technique. The extracted interface state density Dit decreases from 2.92 × 1013 to 1.59 × 1012 cm−2 eV−1 as the energy level depth (EC-ET) increases from 0.29 to 0.50 eV, and then levels off to EC-ET = 0.80 eV. Capacitance-mode deep level transient spectroscopy (C-DLTS) and energy band diagram simulations reveal that deep levels with EC-ET > 0. 83 eV are responsible for the dispersion of capacitances at high temperature (>125 °C) and low frequencies (<1 kHz). A high-resolution transmission electron microscope (TEM) reveals that re-oxidation of the RCA-treated AlGaN barrier surface may be responsible for the relatively high density of shallow states at the LPCVD-SiNx/III-nitride interface.

Capacitance-voltage characterization of interfaces between positive valence band offset dielectrics and wide bandgap semiconductors

A photo-assisted capacitance voltage (C-V) characterization technique for interfaces between positive valence band offset dielectrics (Al2O3, SiO2) and wide bandgap semiconductors is presented. It is shown that the valence band barrier for holes at the interface affects the measurement and a method to extract border trap and interface state density values from the measured C-V curves is suggested. Dielectric-semiconductor interface characterization has been well studied for silicon but the characterization techniques are not transferable to wide bandgap semiconductors, such as GaN and SiC, due to the low minority carrier generation rate. Multiple dielectrics deposited by various techniques have been employed in these devices; but in order to ascertain the most suitable dielectric, an effective characterization technique that works well with dielectrics on wide-bandgap semiconductors is required.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Defect density reduction of the Al 2O 3/GaAs(001) interface by using H 2S molecular beam passivation

The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H 2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications.

H 2S molecular beam passivation of Ge(0 0 1)

A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(0 0 1) using molecular H 2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer.

Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs

The effect of interface states on the current–voltage characteristics in the sub-threshold region of three different types of III–V based transistor architectures has been studied using a drift–diffusion based numerical simulator. Experimentally extracted interface state density profile is included in the simulation to analyze their effect on the sub-threshold response of InGaAs based MOSFETs, MOS HEMTs and tunnel FETs. Based on the Fermi-level position at the oxide/semiconductor interface and the corresponding interface state density ( D it), the sub-threshold response for the three devices can vary, with tunnel FETs having the least sub-threshold degradation due to D it.

High-frequency capacitance–voltage measurement of plasma-enhanced chemical-vapor-deposition-grown SiO2/n-GaN metal-insulator-semiconductor structures

This work reports on the high-frequency capacitance–voltage (C–V) measurements of metal-insulator-semiconductor structures fabricated by depositing SiO2 film on an n-type GaN epitaxial layer. The SiO2 film was grown by plasma-enhanced chemical vapor deposition at 310 °C, and the GaN layer was grown by low-pressure metalorganic chemical vapor deposition on a sapphire substrate. High-frequency C–V measurements have been carried out in darkness with different bias ranges and sweep rates. With a bias between ±20 V, the small flatband shift and the very small hysteresis indicate that the interface trap concentration in the sample is low, and the interface state density is 2.1×1011 eV−1 cm−2. However, a pronounced increase of hysteresis with an extended bias range was observed. When the bias is over ±50 V, the increase of the hysteresis is much larger, indicating the nonuniform distribution of different slow deep states in the structure. The extracted interface state density is in the range of 1012 eV−1 cm−2.

Limitations of conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics

A systematic study of the uncertainties, sensitivity and limitations of the conductance technique for extracting the interface state density of tunneling dielectrics is presented. The methodology required to extract device parameters and interface state density from conductance and capacitance data is reviewed and analyzed. The effect of uncertainties in device parameters on extracted interface state density was determined using experimental results of thin oxides (1.4 nm and 2.0 nm). Modeling was used to indicate the effects of various device parameters on the sensitivity of conductance to changes in interface state density. The effect of uncertainties in insulator capacitance of equivalently thin dielectrics on uncertainties in extracted interface state density is minimal. The effect of uncertainties in series resistance increases with increasing bias towards accumulation. An increase in the series resistance of the device causes reduced sensitivity to changes in interface state density especially for interface states located nearer the majority band edge; increasing tunneling current causes increased uncertainties and reduced sensitivity to changes in interface state density especially for interface states nearer midgap.

Interface states in regrown GaAs p-n junctions by selective molecular beam epitaxy

We report the first evaluation of interface states present in GaAs p-n junctions regrown on a SiO2 masked substrate by selective molecular beam epitaxy. A constant-capacitance deep-level transient spectroscopy (CC-DLTS) method is extended to the regrown p-n junction case, and a technique to distinguish the DLTS signal emerging from bulk and interface states is employed. The extracted interface state density is in good agreement with predictions based on the unified disorder-induced gap state model.

Interface state density in Au- nGaAs Schottky diodes

A method for determining the surface state density in Schottky diodes taking into account both I–V and C–V data while considering the presence of a deep donor level is presented. The model assumes that the barrier height is controlled by the energy distribution of surface states in equilibrium with the metal and the applied potential and does not include, explicitly, an interfacial layer. The model was applied to extract interface state densities of Au- nGaAs guarded Schottky diodes fabricated from bulk and VPE (100) GaAs with carrier conentrations between 3 × 10 15 and 8 × 10 16 cm −3. These diodes exhibited ideality ( n) factors of approximately 1.02 and room temperature saturation current densities ∼10 −8 A/cm 2. This model is in substantial agreement with forward bias measurements over the 77–360°K temperature range investigated, in that a temperature-independent energy distribution of interface states was obtained. In reverse bias the interface state model is most valid with the higher carrier concentration material and at high temperature and low bias voltage. Typical interface state densities from 0.07 eV above the zero bias Fermi level to 0.01 eV below the Fermi level were 2 × 10 13 cm −2 eV −1. The validity of the model under reverse bias is restricted by a non-thermionic reverse current, thought to be enhance field emission from traps.

A method to extract interface state parameters from the MIS parallel conductance technique

A method to extract interface state parameters from the MIS parallel conductance technique