Extra Hardware Overhead Research Articles

A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.

Secure Testable S-box Architecture for Cryptographic Hardware Implementation

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks.

A partial scan design unifying structural analysis and testabilities

To overcome the large extra hardware overhead attendant in full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. Two typical partial scan techniques, based on structural analysis and testabilities, are widely adopted. The structural analysis requires less searching time, however in general the fault coverage is lower. On the other hand, the techniques using testabilities result in higher fault coverage, but require an extraordinary amount of searching time. In this paper we have analysed and unified the strength of techniques using structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flop but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for most ISCAS89 benchmark circuits.

Testable design of multiple-stage OTA-C filters

This paper presents a novel design and test methodology to increase the testability of multistage operational transconductance amplifier and grounded capacitor (OTA-C) filters. As assumed herein, a fault can cause the value of a passive circuit component to deviate from its normal value in order to detect such faults. This deviation causes open-circuit and/or short-circuit effects or changes the operating characteristics of the active components. That is, the catastrophic and parameter deviation faults are considered in this paper. The proposed methodology is also effective in detecting single and multiple faults. Simulation results for the faulty and fault-free circuits are compared to verify the feasibility of our design-for-testability (DFT) structure. The physical layout of a third-order Butterworth OTA-C filter is implemented by the TANNER layout tool. The extra hardware overhead to make the OTA-C filters testable is less than 9%, which is quite a reasonable value for analogue circuits.

A built‐in test for functional testing in semiconductor random access memory

AbstractThe increasing time for functional testing of the logical circuit has become a problem in recent years. As a solution a built‐in test is proposed as a means to make testing easier. In the proposed method, the testing circuit is built in the IC chip, and the test is executed within the chip to verify whether the function is fault‐free. This paper proposes a new built‐in test for the semiconductor memory by considering its internal operation. In the method, all the data from memory cells on the same word‐line can be treated at the same time, using the built‐in test circuit in the chip. As a result, the length of the test sequence is of the order of N1/2, realizing a high‐speed testing. Another feature is that the tests for the memory‐cell array and the decoder can be executed independently, making it possible to cope with the multiple fault in those circuits. The built‐in test circuit can be implemented in a relatively simple way, and the extra hardware overhead becomes almost negligible with the increase of the memory capacity.