External Clock Research Articles

Retrieving geophysical signals from GPS in the La Plata River region

Over the last few years, efforts to model short-term deformations of the Earth’s crust have multiplied. Sudden water level rise can cause sporadic, but significant, motions in the solid Earth’s surface. In this work, we address the problem of retrieving reliable estimates of the vertical displacement of a Global Positioning System (GPS) station located very close to the eastern shore of the La Plata River, during a strong storm surge event. Capturing sub-daily GPS displacements demands an elaborate processing strategy because several highly correlated parameters must be estimated simultaneously. We present a successful strategy that reduces the number of unknowns that have to be estimated simultaneously, by using an empirical model that describes the elastic response of the Earth’s crust to the hydrological load variations. We incorporate this model into the observation equations so that, instead of estimating the station position, we estimate every epoch a single parameter of the empirical model, i.e., the empirical elastic parameter EEP, that is assumed to be a constant of the Earth’s crust in the region of the GPS station. We verify that the estimated parameter agrees well with the value calculated from the CRUST 1.0-A model of the Earth’s crust. The GPS receiver was tied to an external cesium clock, which allowed us to process the data according to two different strategies: (a) estimating the receiver clock error (Δt) as an epoch-wise free parameter, which is equivalent to ignoring the presence of the external clock, and (b) conditioning the variability of that estimate with a small a priori variance compatible with the external clock’s variability. We find that, without having an external atomic clock, the estimation of all the parameters, i.e., the zenith tropospheric delay, Δt, and the EEP, worsens when the GPS station is affected by sub-daily vertical displacements.

64 × 64 GM-APD array-based readout integrated circuit for 3D imaging applications

Using the high sensitivity of the avalanche photodiode (APD) detector operated in the Geiger-mode (GM), an array readout integrated circuit (ROIC) comprising a two-segment time-to-digital converter (TDC) is employed for wide-dynamic time interval measurement, where a 1-bit low-segment TDC is implemented by discriminating a single-phase clock period. The proposed 64 $\times$ 64 GM-APD array ROIC fabricated using Taiwan semiconductor manufacturing company (TSMC) 0.18-$\mu~$m complementary metal oxide semiconductor (CMOS) technology can operate at a maximum frequency of 500 MHz provided by an external phase-locked loop clock. The time resolution is reduced to $<1$ ns along with a maximum range of 4 $\mu~$s; the differential non-linearity (DNL) and integral non-linearity (INL) are restricted to approximately $-$0.15 to 0.15 least significant bit (LSB) and $-$0.3 to 0.32 LSB, respectively; and the power consumption is 490 mW under a frame rate of 20 kHz. The developed ROIC is successfully used in imaging applications in two different ways.

Study on Generating High Frequency Pulses in FPGA

Clock pulse is always generated via crystal vibrator. But in some special conditions that clock pulse circuit is in malfunction, or clock frequency is not high enough, some ingenious implement ways of generating clock pulse in FPGA can solve the problem. In this paper, three methods of generating pulses in FPGA are put forward. The pulses generating are mainly based on short response time of the FPGA logic cells, so the frequency of the pulses is high. Analysis and experiments show that pulses can be generated via FPGA itself other than external clock circuit, and these implement ways of generating clock pulse in FPGA are feasible.

A Spread-Spectrum Mode Enabled Ripple-Based Buck Converter Using a Clockless Frequency Control

Current-mode ripple-based dc–dc converters have become a widely adopted topology due to their inherent advantages of improved dynamic transient response along with a simple current sensing scheme. However, the switching frequency of such converters is a function of the converter’s duty cycle and inherent circuit delays. In this brief, a novel frequency control of a buck converter is proposed through the implementation of a frequency-to-voltage converter that obviates the need for an external clock, and enables both fixed-switching frequency ( ${F} _{\textbf {SW}}$ ) and spread-spectrum modes of operation. A current-mode ripple-based buck converter is implemented in a 180-nm CMOS process for an input voltage of 2.8–4.2 V, output voltage range of 1.3–2.2 V, and load current range of 40–200 mA. In fixed- ${F} _{\textbf {SW}}$ mode, a peak efficiency of 89.4% was achieved at an input voltage of 3.8 V, load current of 200 mA and 1.8 V output voltage, while in spread-spectrum mode, a peak efficiency of 88.2% was achieved for similar conditions. Additionally, in spread-spectrum mode, a 19-dB reduction in peak noise power is observed in the output at the fundamental frequency.

Real‐Time Coseismic Slip Estimation via the GNSS Carrier Phase to Fault Slip Approach: A Case Study of the 2016 Kumamoto Earthquake

AbstractWe investigate the feasibility of Global Navigation Satellite System (GNSS)‐based deformation monitoring that detects coseismic fault slip directly from GNSS carrier phases without conventional positioning analysis. This method, which we call the phase‐to‐slip (PTS) method, does not require high‐quality orbital information because it relies only on changes in azimuthal site‐to‐satellite ranges. With this method, computational costs for real‐time seismic monitoring can be reduced. Here we applied the PTS method to the mainshock of the 2016 Kumamoto earthquake by modifying the original algorithm and using both precise orbits by International GNSS Service (IGS) and broadcast orbits. In both cases, obtained coseismic slip distributions agree well with previous studies. Calculated surface displacements from inferred slip distributions also agree with traditional positioning analysis. These results suggests that the PTS method may be useful as a supplement to currently operated deformation monitoring system, especially when external orbit and clock information are not accessible.

Time-Domain Evaluation Method for Clock Frequency Stability Based on Precise Point Positioning

The Global Navigation Satellite System (GNSS) and GNSS receivers can be used to measure the time-frequency errors of receiver clocks so as to evaluate their frequency stability. The calculation of receiver clock error by single point positioning (SPP) is not highly accurate, resulting in the limited evaluation of clock frequency stability. Therefore, this study proposes a precision point positioning (PPP) evaluation method. In this method, the receiver is driven by an external clock to be evaluated, and the receiver clock error calculated by PPP is used as the measured clock phase error to calculate the Allan variance. The frequency stability of three clocks with different grades (temperature compensated crystal oscillator [TCXO], oven controlled crystal oscillator [OCXO], and rubidium clock) are evaluated with the PPP evaluation method. The PPP evaluation method can evaluate the frequency stabilities of TCXO and OCXO for an average interval of more than 1 s, and the evaluation error of OCXO is less than 1.3 × 10 -11 . As for the rubidium clock, its frequency stability can be evaluated by the PPP evaluation method for an average interval of more than 66 s, and the error is less than 2 × 10 -13 . In general, the PPP evaluation method involves simple operations, achieves high accuracy, and is easily popularized.

Low latency serial communication for MEG II trigger system

In the framework of the upgrade of the MEG experiment a new trigger system with demanding performances in terms of latency was designed. To achieve the goal of 512 ns latency the serial connections between trigger boards have been optimized so that they only rely on serial to parallel shift registers for the data flow, minimizing the amount of logic to be crossed by data. A dedicated Finite State Machine (FSM) was designed to select the sampling point of the serial stream with respect to an external precision clock used by both transmitter and receiver. As a proof of concept a 16 000 channel weighted waveform sum including pedestal suppression, was computed, resulting in 700 ns of latency.

Design of an Ultra-low Power Wireless Temperature Sensor Based on Backscattering Mechanism

In this paper, we propose a passive wireless temperature sensor for long-term and long-range application. A novel architecture of the wireless temperature sensor is proposed based on backscattering mechanism of RFID technology for ultra-low power application. The temperature sensor adopts phase-locked loop-based architecture and can achieve the temperature-digital conversion in frequency domain without any external clock signal. The rectifier employs a gate-boosting scheme to improve the power conversion efficiency. The measurement results show that the proposed wireless temperature sensor obtains a high linearity with a resolution of 0.3 °C/LSB. The measured minimum power dissipation is 2.7 µW, resulting in a maximum operating distance of 34 m under 4 W radiation power.

Cognitions about time affect perception, behavior, and physiology - A review on effects of external clock-speed manipulations.

Our understanding of (altered) time perception may benefit from investigating its potential effects upon other psychological and physiological parameters. To date, however, only a few rather isolated studies have experimentally manipulated the subjective passage of time or the amount of apparently elapsed duration in order to investigate such effects. Based on our review of these studies, first, altered time perception can be induced effectively by means of rigged (accelerated or decelerated) external clocks, second, these clock-speed manipulations remain unnoticed by most participants, and third, several psychological, cognitive, behavioral, and physiological variables can be affected, e.g., fatigue, hunger, pain perception. However, the existing studies on time-perception manipulation do not systematically relate to each other and the underlying mechanisms of the observed effects are poorly understood. Based on cognitive appraisal theories and the given empirical results, we propose a cognitive framework for interpreting and explaining the effects of manipulations of time perception.

A CMOS Timer-Injector Integrated Circuit for Self-Powered Sensing of Time-of-Occurrence

Self-powered sensing of the time-of-occurrence of an event is challenging, because it requires access to a reliable time reference or a synchronized clock. In this paper, we propose for the first time a self-powered integrated circuit that is capable of time-stamping asynchronous mechanical events of interest. The core of the proposed design is the integration of two self-powered modules: 1) a chip-scale Fowler–Nordheim tunneling-based timer array, for generating a precision, relative time reference; and 2) a linear piezoelectricity-driven hot-electron injector acting as a floating-gate memory to record the onset of mechanical events. This paper presents measured results from a $4 \times 4$ fully programmable timer array system-on-chip (SoC) and a linear injector array SoC, both of which have been prototyped in a standard double-poly CMOS process. The synchronization error of the timer array with respect to an external software clock was measured to be less than 1% over a duration of 100 h, and the average accuracy in sensing the time-of-occurrence of the event was measured to be 6.9%. The minimum activation energy of the self-powered system was measured to be 840 nJ (measured for event durations of 1 s), which is significantly lower than the energy that can be harvested from typical mechanical impacts.

RESEARCH IN APPLICATION OF GEODETIC GPS RECEIVERS IN TIME SYNCHRONIZATION

Abstract. In recent years, with the development of satellite orbit and clock parameters accurately determining technology and the popularity of geodetic GPS receivers, Common-View (CV) which proposed in 1980 by Allan has gained widespread application and achieved higher accuracy time synchronization results. GPS Common View (GPS CV) is the technology that based on multi-channel geodetic GPS receivers located in different place and under the same common-view schedule to receiving same GPS satellite signal at the same time, and then calculating the time difference between respective local receiver time and GPST by weighted theory, we will obtain the difference between above local time of receivers that installed in different station with external atomic clock. Multi-channel geodetic GPS receivers have significant advantages such as higher stability, higher accuracy and more common-view satellites in long baseline time synchronization application over the single-channel geodetic GPS receivers. At present, receiver hardware delay and surrounding environment influence are main error factors that affect the accuracy of GPS common-view result. But most error factors will be suppressed by observation data smoothing and using of observation data from different satellites in multi-channel geodetic GPS receiver. After the SA (Selective Availability) cancellation, using a combination of precise satellite ephemeris, ionospheric-free dual-frequency P-code observations and accurately measuring of receiver hardware delay, we can achieve time synchronization result on the order of nanoseconds (ns). In this paper, 6 days observation data of two IGS core stations with external atomic clock (PTB, USNO distance of two stations about 6000 km) were used to verify the GPS common-view theory. Through GPS observation data analysis, there are at least 2–4 common-view satellites and 5 satellites in a few tracking periods between two stations when the elevation angle is 15°, even there will be at least 2 common-view satellites for each tracking period when the elevation angle is 30°. Data processing used precise GPS satellite ephemeris, double-frequency P-code combination observations without ionosphere effects and the correction of the Black troposphere Delay Model. the weighted average of all common-viewed GPS satellites in the same tracking period is taken by weighting the root-mean-square error of each satellite, finally a time comparison data between two stations is obtained, and then the time synchronization result between the two stations (PTB and USNO) is obtained. It can be seen from the analysis of time synchronization result that the root mean square error of REFSV (the difference between the local frequency standard at the mid-point of the actual tracking length and the tracked satellite time in unit of 0.1 ns) shows a linear change within one day, However the jump occurs when jumping over the day which is mainly caused by satellites position being changed due to the interpolation of two-day precise satellite ephemeris across the day. the overall trend of time synchronization result is declining and tends to be stable within a week-long time. We compared the time synchronization results (without considering the hardware delay correction) with those published by the International Bureau of Weights and Measures (BIPM), and the comparing result from a week earlier shows that the trend is same but there is a systematic bias which was mainly caused by hardware delays of geodetic GPS receiver. Regardless of the hardware delay, the comparing result is about between 102 ns and 106 ns. the vast majority of the difference within 2 ns but the difference of individual moment does not exceed 4ns when taking into account the systemic bias which mainly caused by hardware delay. Therefore, it is feasible to use the geodetic GPS receiver to achieve the time synchronization result in nanosecond order between two stations which separated by thousands kilometers, and multi-channel geodetic GPS receivers have obvious advantages over single-channel geodetic GPS receivers in the number of common-viewing satellites. In order to obtain higher precision (e.g sub-nanosecond order) time synchronization results, we shall take account into carrier phase observations, hardware delay ,and more error-influencing factors should be considered such as troposphere delay correction, multipath effects, and hardware delays changes due to temperature changes.

A CMOS Self-Contained Quadrature Signal Generator for SoC Impedance Spectroscopy.

This paper presents a low-power fully integrated quadrature signal generator for system-on-chip (SoC) impedance spectroscopy applications. It has been designed in a 0.18 μm-1.8 V CMOS technology as a self-contained oscillator, without the need for an external reference clock. The frequency can be digitally tuned from 10 to 345 kHz with 12-bit accuracy and a relative mean error below 1.7%, thus supporting a wide range of impedance sensing applications. The proposal is experimentally validated in two impedance spectrometry examples, achieving good magnitude and phase recovery results compared to the results obtained using a commercial LCR-meter. Besides the wide frequency tuning range, the proposed programmable oscillator features a total power consumption lower than 0.77 mW and an active area of 0.129 mm2, thus constituting a highly suitable choice as stimulation module for instrument-on-a-chip devices.

Mass-correlated rotational Raman spectra with high resolution, broad bandwidth, and absolute frequency accuracy

We present mass-correlated rotational alignment spectroscopy, based on the optical excitation of a coherent rotational quantum wave and the observation of temporal wave interferences in a mass spectrometer. Combined electronic and opto-mechanical delays increased the observation time and energy resolution by an order of magnitude compared with preceding time-domain measurements. Rotational transition frequencies were referenced to an external clock for accurate absolute frequency measurements. Rotational Raman spectra for six naturally occurring carbon disulfide isotopologues were resolved with 3 MHz resolution over a spectral range of 500 GHz. Rotational constants were determined with single-kilohertz accuracy, competitive with state-of-the-art frequency domain measurements.

Arbitrary digital pulse sequence generator with delay-loop timing.

We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to two clock cycles. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate its capability to produce temporal delays ranging from tens of nanoseconds to hundreds of seconds, with 24 ns timing granularity and linear scaling of delay with respect to the number of delay loop iterations. The generator is optionally synchronized with an external clock source to provide 100 ps jitter and overall sequence repeatability within the whole temporal range. The generator is fully programmable and able to produce digital sequences of high complexity. The concept of the generator can be implemented using different microcontrollers and applied for controlling of various optical, atomic, and nuclear physics measurement setups.

A 1.2V Self-Referenced Temperature Sensor With a Time-Domain Readout and a Two-Step Improvement on Output Dynamic Range

A self-referenced temperature sensor with a time-domain readout and a two-step improvement on output dynamic range is presented in this paper. The proposed temperature sensor utilizes BJTs to generate temperature dependent/independent currents, which are converted to digital bits using a ring-oscillator-based time-domain readout scheme. A novel two-step improvement on output dynamic range is proposed to improve the power-efficiency and simplify the hardware design with a high conversion rate. Furthermore, the adopted process compensation strategy and the self-referenced readout scheme make the whole temperature sensor robust to process and supply variations. Fabricated in a standard 0.13- $\mu \text{m}$ CMOS process, the proposed temperature sensor occupies a die area of 0.06 mm2 and consumes 9.92 nJ per conversion at a conversion rate of 75 kSa/s. After one-point calibration at 20 °C, the sensor achieves inaccuracies of −2.88 °C/+2.71 °C and −1.7 °C/1.36 °C from −20 °C to 100 °C, with and without systematic nonlinearity removal, respectively. It shows an average supply sensitivity of 0.0136 °C/mV from 1.05 V to 1.4 V without any external reference clock or voltage regulators.

DPWM techniques in digitally controlled, EMI compliant DC-DC converters

This paper aims to present a combined, DPWM based control method and spectrum flattening technique of a mid-power range DC-DC converter. The research goal was to obtain sustainable results in both switching control and EMI compliance, using one 8 or 16 bits RISC MCU as main control unit running a performance- and speed-optimized firmware. This approach describes a hybrid method preserving the good dynamic performances of an analog switching regulator controller and adding the flexibility of controlling the output voltage by adjusting the duty cycle value of a DPWM signal and thus controlling the average voltage value of the signal applied in the feedback circuit of a DC-DC converter. Beside the feedback control of the DC-DC converter an active EMI reduction technique applies on this design by taking advantage on the constant-frequency, forced-continuous current mode architecture of the switching regulator controller, which allows its frequency to be synchronized with an external control clock dithered by a software implemented pseudo-random sequence generator. All this efforts concludes in reducing the noise power considerably at the main peak and at the next peaks.

Optically driven ultra-stable nanomechanical rotor

Nanomechanical devices have attracted the interest of a growing interdisciplinary research community, since they can be used as highly sensitive transducers for various physical quantities. Exquisite control over these systems facilitates experiments on the foundations of physics. Here, we demonstrate that an optically trapped silicon nanorod, set into rotation at MHz frequencies, can be locked to an external clock, transducing the properties of the time standard to the rod’s motion with a remarkable frequency stability fr/Δfr of 7.7 × 1011. While the dynamics of this periodically driven rotor generally can be chaotic, we derive and verify that stable limit cycles exist over a surprisingly wide parameter range. This robustness should enable, in principle, measurements of external torques with sensitivities better than 0.25 zNm, even at room temperature. We show that in a dilute gas, real-time phase measurements on the locked nanorod transduce pressure values with a sensitivity of 0.3%.

Mode-locked fibre lasers with an adjustable drop-shaped cavity

We report the first implementation of a new cavity topology for mode-locked fibre lasers. This new ‘drop-shaped’ cavity topology employs a dual-fibre optical collimator and allows for a relatively simple cavity design with continuously adjustable length. It combines the advantages of the conventional ring cavity topology with the adjustment capabilities of hybrid ring-linear cavities (e.g. σ-cavities). Reliable femtosecond pulsed lasing was demonstrated in the experimental drop-shaped Er-doped fibre lasers, which were mode-locked in two different ways—by exploiting nonlinear polarisation evolution (NPE) and by means of a semiconductor saturable absorber. In the case of NPE-based mode locking, the shortest pulse duration was ~450 fs. The pulse repetition rate could be continuously varied within ±3 kHz around ~25 MHz in the NPE-mode-locked lasers when the distance between the dual-fibre optical collimator and the cavity mirror was adjusted. This feature could, in principle, allow active stabilisation of the pulse repetition rate. Thus, mode-locked fibre lasers with the proposed drop-shaped cavity topology could be applied in metrology and other fields where a high stability of pulse repetition rate or its synchronization with an external clock is required.

An Ultralow Power Time-Domain Temperature Sensor With Time-Domain Delta–Sigma TDC

Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is using a time-domain delta–sigma $(\Delta\Sigma)$ modulator. This type of TDC with $\Delta\Sigma$ modulator can achieve higher resolution by increasing the oversampling ratio, with the advantages of low area and low power consumption. To increase the accuracy by producing true temperature-independent time delay, an external reference clock is utilized, instead of temperature-independent inverter cells, for robust operations. The measured temperature sensors demonstrated a minimum power consumption of 480 nW and a resolution under 0.1 °C. The $3\sigma$ error of the sensor is ±0.99 °C over −20 °C–80 °C temperature range from ten-sample measurement results. The chip area is 0.089 mm2 using a Dongbu 0.18- $\mu\mbox{m}$ CMOS process. The conversion rate is 1.25 samples/s.

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13–0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.