Execution Overhead Research Articles

The distributed virtual shared-memory system based on the InfiniBand architecture

Even though there have been strong research activities about distributed virtual shared-memory (DVSM) systems, their architectures have been not widely used in current high-performance computing markets. The reason is that the previously introduced DVSM systems use conventional interconnection technologies like Ethernet, which incurs high execution overhead due to process interruption at data communication for memory consistency. In this paper, we present the DVSM architecture based on the next generation of an interconnection technique, the InfiniBand Architecture (IBA). Because the IBA supports shared-memory programming semantics by means of remote direct-memory access (RDMA) and atomic operations in hardware, we can minimize the communication overhead for memory consistency on the DVSM system. For characterizing multithreaded applications on our IBA-based DVSM system, we examined two different shared-memory programming models, i.e. SPMD and OpenMP benchmarks. We show that our DVSM to use full features of the IBA can improve the performance significantly over the IPoIB-based DVSM system in all benchmarks, and also comparable to the bus-based shared-memory multiprocessor system in some benchmarks.

Efficient and flexible architectural support for dynamic monitoring

Recent impressive performance improvements in computer architecture have not led to significant gains in the case of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root cause of a bug. Moreover, program execution typically slows down significantly, often by 10--100 times.To address this problem, this paper introduces the intelligent watcher (iWatcher) , a novel architectural scheme to monitor dynamic execution automatically, flexibly, and with minimal overhead. iWatcher associates program-specified monitoring functions with memory locations. When any such location is accessed, the monitoring function is automatically triggered with low overhead. To further reduce overhead and support rollback, iWatcher can optionally leverage thread-level speculation (TLS). The iWatcher architecture can be used to detect various bugs, including buffer overflow, accessing freed locations, memory leaks, stack-smashing and value-invariant violations. To evaluate iWatcher, we use seven applications with various real and injected bugs. Our results show that iWatcher detects many more software bugs than Valgrind, a well-known open-source bug detector. Moreover, iWatcher only induces a 0.1--179% execution overhead, which is orders of magnitude less than Valgrind. Our sensitivity study shows that even with 20% of the dynamic loads monitored in a program, iWatcher adds only 72--182% overhead. Finally, TLS is effective at reducing overheads for programs with substantial monitoring.

Partitioning Medical Image Databases for Content-based Queries on a Grid

In this paper we study the impact of executing a medical image database query application on the grid. For lowering the total computation time, the image database is partitioned into subsets to be processed on different grid nodes. A theoretical model of the application complexity and estimates of the grid execution overhead are used to efficiently partition the database. We show results demonstrating that smart partitioning of the database can lead to significant improvements in terms of total computation time. Grids are promising for content-based image retrieval in medical databases.

Profiling soft-core processor applications for hardware/software partitioning

In this paper, we present an efficient approach to HW/SW partitioning of applications targeted for embedded softcore SoPC and programmable logic. The methodology is based on the iterative performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations. The main focus is on adequate profiling of arbitrary SW code regions (function or single instruction level) with clock-cycle accuracy without introducing additional execution overhead. In order to support the profiling for partitioning, we have developed the COMET Profiler tool. The performance analysis and estimation in the simulation and implementation domains are supported, necessitating no design and implementation of HW co-processing blocks for the partitioning evaluation. The design process is illustrated with two case studies.

IWatcher

Recent impressive performance improvements in computer architecturehave not led to significant gains in ease of debugging.Software debugging often relies on inserting run-time softwarechecks. In many cases, however, it is hard to find the root causeof a bug. Moreover, program execution typically slows down significantly,often by 10-100 times.To address this problem, this paper introduces the IntelligentWatcher (iWatcher), novel architectural support to monitor dynamicexecution with minimal overhead, automatically, and flexibly.iWatcher associates program-specified monitoring functionswith memory locations. When any such location is accessed, themonitoring function is automatically triggered with low overhead.To further reduce overhead and support rollback, iWatcher canleverage Thread-Level Speculation (TLS). To test iWatcher, we useapplications with various bugs. Our results show that iWatcher detectsmany more software bugs than Valgrind, a well-known open-sourcebug detector. Moreover, iWatcher only induces a 4-80%execution overhead, which is orders of magnitude less than Valgrind.Even with 20% of the dynamic loads monitored in a program,iWatcher adds only 66-174% overhead. Finally, TLS is effective atreducing overheads for programs with substantial monitoring.

On-line scheduling of scalable real-time tasks on multiprocessor systems

The computation time of scalable tasks depends on the number of processors allocated to them in multiprocessor systems. As more processors are allocated to a scalable task, the overall computation time of the task decreases but the total amount of processors’ time devoted to the execution of the task, called workload, increases due to parallel execution overhead. In this paper, we propose a task scheduling algorithm that utilizes the property of scalable tasks for on-line and real-time scheduling. In the proposed algorithm, the total workload of all scheduled tasks is reduced by managing processors allocated to the tasks as few as possible without missing their deadlines. As a result, the processors in the system have less load to execute the scheduled tasks and can execute more newly arriving tasks before their deadlines. Simulation results show that the proposed algorithm performs significantly better than the conventional algorithm based on a fixed number of processors to execute each task.

Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture

This paper presents a mapping scheme of an optimized octree-based ray tracing algorithm and its implementation on a SIMD reconfigurable architecture, MorphoSys, with appropriate hardware incorporated. A two-level SIMD mapping scheme for ray tracing is chosen to get better trade-off between coherence exploitation efficiency and bandwidth requirements. We apply a SIMD octree traversal algorithm that supports ray traversals of any origins and directions. Moreover, we have applied the bottom-up traversal order for shadow and reflection rays to avoid unnecessary testing. The memory overhead of the parallel execution of ray tracing in SIMD systems is analyzed to direct memory optimization. Pre-fetching is utilized to hide data fetch latency behind the computation. A Spatial Partitioning Tree buffer reduces the latency due to the interleaved accesses to the shared memory. It also dynamically exploits ray coherence to save memory bandwidth. A Pointer Update Unit and a Pointer Buffer are combined to remove the overhead resulted from pointer-calculations and stack pushes during the parallel depth-first-traversal process. The associated hardware cost is less than 2% of the whole system. In order to include diffuse effects into the output, we apply spherical harmonic. Post-synthesis simulation shows that the target chip is estimated to be 33 mm 2 and consumes less than 1 W in the worst case. Cycle-accurate simulation demonstrates that interactive ray tracing for medium-sized scenes is achieved on MorphoSys.

Safe Execution of Unreliable Software

We introduce a method, Lightweight Privilege Separation, enabling safe execution of unreliable software. Our method introduces no new software vulnerabilities and is fairly easy to implement. Furthermore, we show by experiments that the execution overhead is in the order of milliseconds per execution of the unreliable process at hand. We compare our method with earlier attempts of privilege separation such as OpenSSH. The paper concludes with a discussion on generalizations of our approach in the form of abstract machines and their interpreters.

Compiling java for low-end embedded systems

The production of embedded systems is continuously increasing, but developing reusable software for such systems is notoriously difficult, in particular in the case of low-end embedded systems based on 16-bit or 8-bit processors. We have developed a compilation system for executing Java byte code on low-end embedded systems, and we demonstrate how this system permits object-oriented programming techniques to be used on devices with only a few hundred bytes of RAM and a few kilobytes of ROM.We analyze the execution overheads of using object-orien\-ted programming on low-end embedded systems. Based on the conclusion that memory consumption is the major obstacle, we show how the configuration features and optimizations integrated into our compiler can be used to significantly reduce memory requirements. In particular, we use a novel approach based on Java interfaces to control integration of Java programs with the hardware, and demonstrate how aggressive whole-program optimization can significantly reduce the size of the compiled program.

Compiler techniques for the distribution of data and computation

This paper presents a new method that can be applied by a parallelizing compiler to find, without user intervention, the iteration and data decompositions that minimize communication and load imbalance overheads in parallel programs targeted at NUMA architectures. One of the key ingredients in our approach is the representation of locality as a locality-communication graph (ICG) and the formulation of the compiler technique as a mixed integer nonlinear programming (MINLP) optimization problem on this graph. The objective function and constraints of the optimization problem model communication costs and load imbalance. The solution to this optimization problem is a decomposition that minimizes the parallel execution overhead. This paper summarizes the process of how the compiler extracts the locality information from a nonannotated code and focuses on how this compiler can derive the optimization problem, solve it, and generate the parallel code with the automatically selected iteration and data distributions. In addition, we include a discussion about our model and the solutions - the decompositions - that it provides. The approach presented in the paper is evaluated using several benchmarks. The experimental results demonstrate that the MINLP formulation does not increase compilation time significantly and that our framework generates very efficient iteration/data distributions for a variety of NUMA machines.

Indirect VLIW memory allocation for the ManArray multiprocessor DSP

The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManArray family of multiprocessor digital signal processors (DSP) provides a scalable alternative to the wide instruction busses usually required in a multiprocessor VLIW DSP. The ManArray processors indirectly access VLIWs from small caches of VLIWs localized in each processing element. With this work, we present an algorithm to perform 1) iVLIW instruction memory allocation on multiple processing elements to minimize instruction memory requirements and 2) scheduling of the iVLIW setup instructions to minimize execution overhead. We present preliminary experimental results that demonstrate the effectiveness of our approach.

Data collection and restoration for heterogeneous process migration

AbstractThis study presents a practical solution for data collection and restoration to migrate a process written in high‐level stack‐based languages such as C and Fortran over a network of heterogeneous computers. We first introduce a logical data model, namely the Memory Space Representation (MSR) model, to recognize complex data structures in process address space. Then, novel methods are developed to incorporate the MSR model into a process, and to collect and restore data efficiently. We have implemented prototype software and performed experiments on different programs. Experimental and analytical results show that: (1) a user‐level process can be migrated across different computing platforms; (2) semantic information of data structures in the process's memory space can be correctly collected and restored; (3) costs of data collection and restoration depend on the complexity of the MSR graph in the memory space and the amount of data involved; and (4) the implantation of the MSR model into the process is not a decisive factor of incurring execution overheads. With appropriate program analysis, we can practically achieve low overhead. Copyright © 2002 John Wiley & Sons, Ltd.

Profile-directed optimization of event-based programs

Events are used as a fundamental abstraction in programs ranging from graphical user interfaces (GUIs) to systems for building customized network protocols. While providing a flexible structuring and execution paradigm, events have the potentially serious drawback of extra execution overhead due to the indirection between modules that raise events and those that handle them. This paper describes an approach to addressing this issue using static optimization techniques. This approach, which exploits the underlying predictability often exhibited by event-based programs, is based on first profiling the program to identify commonly occurring event sequences. A variety of techniques that use the resulting profile information are then applied to the program to reduce the overheads associated with such mechanisms as indirect function calls and argument marshaling. In addition to describing the overall approach, experimental results are given that demonstrate the effectiveness of the techniques. These results are from event-based programs written for X Windows, a system for building GUIs, and Cactus, a system for constructing highly configurable distributed services and network protocols.

A framework for reducing the cost of instrumented code

Instrumenting code to collect profiling information can cause substantial execution overhead. This overhead makes instrumentation difficult to perform at runtime, often preventing many known offline feedback-directed optimizations from being used in online systems. This paper presents a general framework for performing instrumentation sampling to reduce the overhead of previously expensive instrumentation. The framework is simple and effective, using code-duplication and counter-based sampling to allow switching between instrumented and non-instrumented code. Our framework does not rely on any hardware or operating system support, yet provides a high frequency sample rate that is tunable, allowing the tradeoff between overhead and accuracy to be adjusted easily at runtime. Experimental results are presented to validate that our technique can collect accurate profiles (93-98% overlap with a perfect profile) with low overhead (averaging 6% total overhead with a naive implementation). A Jalape~ no-specific optimization is also presented that reduces overhead further, resulting in an average total overhead of 3%.

The implementation of the ecosystem module of a coastal environmental model: Port Phillip Bay, Australia

When implemented as a computer program, an ecosystem model is only a part of a larger programming environment. This programming environment includes other programs, non-model program components, program design rules, data files, and associated analysis analytical tools. These components should be divided to allow programmers to focus on their areas of expertise, but must then be rejoined in such a way as to minimise debugging and execution overheads. We describe this larger programming environment as it surrounds a model of the ecosystem of Port Phillip Bay, Australia. The ecosystem model requires a transport model to allow spatial modelling; this transport model uses currents from a computationally intensive hydrodynamic model. Implementation of the ecosystem model also requires non-model code, such as routines to initialise parameters or the integration method. Their design determines program reliability and performance. A modular structure allows different parts of the model to be independently modified; this makes for efficient programming. We describe formal design rules used to enhance readability and information content of the model's parameter names. To execute, the model must access data files and a record of the run must be kept — a Unix shell program serves both these functions. The data files may require software tools for generation or manipulation. Output from the model also requires post-processing for visualisation and analysis. The model is thus only a part of a network of software, whose development must be coordinated to ensure reliability and efficiency.

Chameleon: a software infrastructure for adaptive fault tolerance

This paper presents Chameleon, an adaptive infrastructure, which allows different levels of availability requirements to be simultaneously supported in a networked environment. Chameleon provides dependability through the use of special ARMORs-Adaptive. Reconfigurable, and Mobile Objects for Reliability-that control all operations in the Chameleon environment. Three broad classes of ARMORs are defined: 1) Managers oversee other ARMORs and recover from failures in their subordinates. 2) Daemons provide communication gateways to the ARMORs at the host node. They also make available a host's resources to the Chameleon environment. 3) Common ARMORs implement specific techniques for providing application-required dependability. Employing ARMORs, Chameleon makes available different fault-tolerant configurations and maintains run-time adaptation to changes in the availability requirements of an application. Flexible ARMOR architecture allows their composition to be reconfigured at run-time, i.e., the ARMORs may dynamically adapt to changing application requirements. In this paper, we describe ARMOR architecture, including ARMOR class hierarchy, basic building blocks, ARMOR composition, and use of ARMOR factories. We present how ARMORs can be reconfigured and reengineered and demonstrate how the architecture serves our objective of providing an adaptive software infrastructure. To our knowledge, Chameleon is one of the few real implementations which enables multiple fault tolerance strategies to exist in the same environment and supports fault-tolerant execution of substantially off-the-shelf applications via a software infrastructure only. Chameleon provides fault tolerance from the application's point of view as well as from the software infrastructure's point of view. To demonstrate the Chameleon capabilities, we have implemented a prototype infrastructure which provides set of ARMORs to initialize the environment and to support the dual and TMR application execution modes. Through this testbed environment, we measure the execution overhead and recovery times from failures in the user application, the Chameleon ARMORs, the hardware, and the operating system.

A Linux kernel module implementation of restricted Ada tasking

An Ada tasking kernel is implemented as a layer beneath the Linux operating system on a PC-compatible machine. This implementation is derived from Yodaiken's Real-Time Linux kernel, with new scheduling and synchronization primitives introduced specifically to support the GNAT Ada runtime system. Primitive operations for real-time Ada tasks are directly implemented on top of the underlying hardware in the form of a loadable Linux kernel module. This design not only reduces execution overhead and improves control over execution timing for tasks, but also opens the door for a simple restricted-tasking runtime system that could be certified for safety-critical applications.

Analysis of failure recovery schemes for distributed shared-memory systems

Checkpoint and rollback recovery is a technique used to minimise the loss of computation when failures occur. When a process rolls back and re-executes from the last checkpoint, the cost (loss) incurred by redoing the lost computation may be larger than that to execute the original computation. In addition to completion time delay, other performance metrics (e.g. user's satisfaction in real-time on online transaction applications) may also degrade by unexpected failure and recovery. The paper determines how redo overhead factor for unexpected execution overhead affects the performance of recovery scheme. It analyses the performance of three recoverable schemes (incorporating redo overhead factor): multiple fault-tolerant scheme using checkpointing and rollback recovery, single fault-tolerant scheme, and a two-level scheme.

Exploiting the parallelisation inherent in the windowing approach to Monte Carlo energy perturbation calculations

A parallel version of a Monte Carlo free energy difference code has been implemented to exploit the potential for parallelisation inherent in the free energy perturbation windowing procedure. Since all the windows are run in parallel, the major overhead compared with the serial implementation is the requirement to increase the equilibration for each window from 10 6 configurations to 3 × 10 6 configurations (10 6 configurations were used for data collection for each window). For the perturbation of nitroimidazoles to their radical anions in a box of 500 water molecules, the parallel code gives essentially identical free energy of hydration differences to the serial code. The 64 processor CRAY T3D version of the code has an execution overhead of only 25% compared with the single processor version, suggesting that this approach has great potential. In particular, the approach could be combined with approaches to parallelise the non-bonded interactions, permitting parallelisation over several thousand processors.

Thread- and Process-based Implementations of the pSystem Parallel Programming Environment

Run-time work distribution in parallel programming systems is usually accomplished through the use of dynamic scheduling heuristics. Their sensitivity to run-time information such as global work-load, task granularity, data dependencies, locality of information, among others, is essential when trying to optimize performance. Adaptive schedulers that base their decisions on feed-back from the system are therefore of special importance. We have developed and used a general purpose parallel programming system, the pSystem, that also served as a test-bed environment on which we have experimented and studied the performance of distinct scheduling heuristics. Currently, we have two versions of the system: one based on Unix processes; and the other on Solaris threads. Threads (particularly user-level threads) are usually associated with low execution overheads, since they require minimal interaction with the operating system kernel. This suggests that lower grain parallelism may be more effectively exploited with a thread-based parallel programming system. Performance analysis of both implementations over a set of well known benchmarks, with various schedulers, shows that threads scale better under higher system loads and/or when the granularity of the tasks being executed is below a given threshold value. This paper starts with a description of the design and implementation of the pSystem computational model, followed by a detailed description of several experiments and the analysis of their results. © 1997 John Wiley & Sons, Ltd.