Execution Overhead Research Articles

Scientific computing with Google App Engine

We investigate the potential of Google App Engine (GAE) for scientific computing. We designed a generic master–slave framework that enables implementation and integration of new algorithms by instantiating one interface and two abstract classes. Applications are dynamically scheduled, executed, and monitored by the framework on the Google infrastructure, including a fault tolerant resubmission mechanism upon certain failures. We describe the implementation of a parallel rank sort algorithm using our framework and analyse the speedup, the execution overheads, and the cost of executing it on the Google Cloud infrastructure. Experimental results show that important speedup can be obtained from using GAE, especially for embarrassingly parallel Monte Carlo simulations. The two main obstacles that hinder the performance of applications on GAE are the resource quotas upon free use (especially the 30 s sequential execution time limit) and the middleware overheads. Cost-wise, GAE offers opportunities for cheaper computation due to the CPU cycle-based payment granularity, as opposed to the hourly billing intervals of other providers such as Amazon EC2.

다중 방송 채널에 데이터 할당을 위한 두 단계 저장소-적재 알고리즘

In data broadcasting systems, servers continuously disseminate data items through broadcast channels, and mobile client only needs to wait for the data of interest to present on a broadcast channel. However, because broadcast channels are shared by a large set of data items, the expected delay of receiving a desired data item may increase. This paper explores the issue of designing proper data allocation on multiple broadcast channels to minimize the average expected delay time of all data items, and proposes a new data allocation scheme named two level bin-packing(TLBP). This paper first introduces the theoretical lower-bound of the average expected delay, and determines the bin capacity based on this value. TLBP partitions all data items into a number of groups using bin-packing algorithm and allocates each group of data items on an individual channel. By employing bin-packing algorithm in two step, TLBP can reflect a variation of access probabilities among data items allocated on the same channel to the broadcast schedule, and thus enhance the performance. Simulation is performed to compare the performance of TLBP with three existing approaches. The simulation results show that TLBP outperforms others in terms of the average expected delay time at a reasonable execution overhead.

A scheme for reliable real‐time messaging with bounded delays

SUMMARYNetwork‐based real‐time computing applications that require tightly bounded end‐to‐end delays have been increasing at a steady rate in recent years. A messaging layer that yields tight bounds on the latencies in detecting message losses and enables the application layer to initiate a timely recovery action has thus become highly desirable. In this paper, we present a new reliable real‐time messaging scheme called the Delay‐Bounded Reliable Messaging Scheme (DB‐RMS) that is aimed at meeting such requirements. It is built on top of the User Datagram Protocol sub‐layer. DB‐RMS provides multiple service options, each with different fault detection/recovery capabilities and different costs in terms of the execution overhead. This feature makes DB‐RMS suitable for a variety of applications. In this paper, the DB‐RMS service options and the corresponding support protocols are presented first followed by a formal analysis on the detection and reaction latency bounds under various service options. A messaging layer prototype using DB‐RMS has been implemented. To demonstrate the practice of the DB‐RMS, we implemented a clock synchronization algorithm for 802.11 wireless local area networks on top of the DB‐RMS messaging layer. Performance measurements of the prototype implementation have been taken, and the positive results obtained are also presented. Copyright © 2011 John Wiley & Sons, Ltd.

EXPLOITING INSTRUCTION REUSE TO IMPROVE THE PERFORMANCE OF DUAL INSTRUCTION EXECUTION

Dual instruction execution (DIE) is an effective instruction-level temporal redundancy technique to improve the datapath reliability against transient errors for superscalar microprocessors. However, previous study shows that the performance overhead of dual instruction execution on an out-of-order core is substantial, primarily due to the serious resource contention problems such as the ALU bandwidth. In this paper, we propose a novel approach to reducing the performance overhead of DIE without compromising the datapath reliability. In the proposed scheme, both the primary and the duplicate instructions of DIE can exploit the ECC-protected instruction reuse buffer (IRB) for mitigating the resource contention of DIE by minimizing the number of dynamic instructions executed, leading to better performance without impacting the reliability of DIE. Our experiments indicate that the proposed approach can reduce the performance loss of dual instruction execution by up to 70.8%, with 51.1% on average, and can reduce the performance loss of DIE–IRB by up to 17.2%, with 7.1% on average, while providing reliability comparable to DIE or DIE–IRB.

Metadata Distribution and Consistency Techniques for Large-Scale Cluster File Systems

Most supercomputers nowadays are based on large clusters, which call for sophisticated, scalable, and decentralized metadata processing techniques. From the perspective of maximizing metadata throughput, an ideal metadata distribution policy should automatically balance the namespace locality and even distribution without manual intervention. None of existing metadata distribution schemes is designed to make such a balance. We propose a novel metadata distribution policy, Dynamic Dir-Grain (DDG), which seeks to balance the requirements of keeping namespace locality and even distribution of the load by dynamic partitioning of the namespace into size-adjustable hierarchical units. Extensive simulation and measurement results show that DDG policies with a proper granularity significantly outperform traditional techniques such as the Random policy and the Subtree policy by 40 percent to 62 times. In addition, from the perspective of file system reliability, metadata consistency is an equally important issue. However, it is complicated by dynamic metadata distribution. Metadata consistency of cross-metadata server operations cannot be solved by traditional metadata journaling on each server. While traditional two-phase commit (2PC) algorithm can be used, it is too costly for distributed file systems. We proposed a consistent metadata processing protocol, S2PC-MP, which combines the two-phase commit algorithm with metadata processing to reduce overheads. Our measurement results show that S2PC-MP not only ensures fast recovery, but also greatly reduces fail-free execution overheads.

On Supporting Rapid Thermal Analysis

Detailed thermal analysis is usually performed exclusively at design time since it is a computationally intensive task. In this paper, we introduce a novel methodology for fast, yet accurate, thermal analysis. The introduced methodology is software supported by a new open source tool that enables hierarchical thermal analysis with adaptive levels of granularity. Experimental results prove the efficiency of our approach since it leads to average reduction of the execution overhead up to 70% with a penalty in accuracy ranging between 2% and 8%.

Two New Protocols for Fault Tolerant Agreement

The paper attempts to handle failures effectively, while reaching agreement, in a distributed transaction processing system. The standard protocols such as BFTDC [3], Zyzzyva [4] and PBFT [5] handle the problem to a greater extent. However, the limitation with these protocols is that they incur increased message overhead as well as large latency. Moreover, the nodes are evacuated from the transaction system after being declared faulty. We propose a novel proactive based agreement which identifies the tentative failures in the system. To improve the failure resiliency with minimum execution overhead, we also propose an optimized reactive view change mechanism. Both mechanisms have been analyzed and compared. The dynamic analysis of the protocol reflects that, in a faulty scenario, the proactive approach is computationally more efficient with reduced latency as compared to reactive one. Moreover, unlike PBFT and BFTDC, our agreement protocol runs in two phases, which leads to reduced message overhead and total execution time. The protocol treats the fail-silent (i.e. crashed) nodes in the system.

Simultaneous Virtual-Machine Logging and Replay

This paper proposes simultaneous virtual-machine logging and replay. It performs logging and replay simultaneously on the same machine through the use of two virtual machines, one for the primary execution and the other for the backup execution. While the primary execution produces the execution history, the backup execution consumes the history by replaying it. The size of an execution log can be limited to a certain size; thus, huge storage devices becomes unnecessary. We developed such a logging and replaying feature in a VMM. It can log and replay the execution of the Linux operating system. Our experiment results show the overhead of the primary execution is only fractional.

Proactive and Reactive View Change for Fault Tolerant Byzantine Agreement

Problem statement: Dealing with arbitrary failures effectively, while reaching agreement, remains a major operational challenge in distributed transactions. In the contemporary literature, standard protocols such as Byzantine Fault Tolerant Distributed Commit and Practical Byzantine Fault Tolerance handles the problem to a greater extent. However, the limitation with these protocols is that they incur increased message overhead as well as large latency. Approach: To improve the failure resiliency with minimum execution overhead, we propose two new protocols based on proactive view change and reactive view change. Also, both approaches have been analyzed and compared. Results: Our dynamic analysis reflects that, in a faulty scenario, the proactive approach is computationally more efficient with reduced latency as compared to reactive one. Conclusion/Recommendations: Moreover, unlike PBFT and BFTDC, our agreement protocol runs in two phases, which leads to reduced message overhead and total execution time.

Efficient scheme of verifying integrity of application binaries in embedded operating systems

Currently, embedded systems have been widely used for ubiquitous computing environments including digital setup boxes, mobile phones, and USN (Ubiquitous Sensor Networks). The significance of security has been growing as it must be necessarily embedded in all these systems. Up until now, many researchers have made efforts to verify the integrity of applied binaries downloaded in embedded systems. The research of problem solving is organized into hardware methods and software-like methods. In this research, the basic approach to solving problems from the software perspective was employed. From the software perspective, unlike in the existing papers (Seshadri et al., Proc. the IEEE symposium on security and privacy, 2004; Seshadri et al., Proc. the symposium on operating systems principals, 2005) based on the standardized model (TTAS.KO-11.0054. http://www.tta.or.kr 2006) publicized in Korea, there is no extra verifier and conduct for the verification function in the target system. Contrary to the previous schemes (Jung et al. http://ettrends.etri.re.kr/PDFData/23-1_001_011.pdf , 2008; Lee et al., LNCS, vol. 4808, pp. 346---355, 2007), verification results are stored in 1 validation check bit, instead of storing signature value for application binary files in the i-node structure for the purpose of reducing run-time execution overhead. Consequently, the proposed scheme is more efficient because it dramatically reduces overhead in storage space, and when it comes to computing, it performs one hash algorithm for initial execution and thereafter compares 1 validation check bit only, instead of signature and hash algorithms for every application binary. Furthermore, in cases where there are frequent changes in the i-node structure or file data depending on the scheme application, the scheme can provide far more effective verification performance compared to the previous schemes.

Approximation of Generalized Processor Sharing With Interleaved Stratified Timer Wheels

This paper presents Interleaved Stratified Timer Wheels as a novel priority queue data structure for traffic shaping and scheduling in packet-switched networks. The data structure is used to construct an efficient packet approximation of general processor sharing (GPS). This scheduler is the first of its kind by combining all desirable properties without any residual catch. In contrast to previous work, the scheduler presented here has constant and near-optimal delay and fairness properties, and can be implemented with O(1) algorithmic complexity, and has a low absolute execution overhead. The paper presents the priority queue data structure and the basic scheduling algorithm, along with several versions with different cost-performance trade-offs. A generalized analytical model for rate-controlled rounded time-stamp schedulers is developed and used to assess the scheduling properties of the different scheduler versions.

Structure-driven optimizations for amorphous data-parallel programs

Irregular algorithms are organized around pointer-based data structures such as graphs and trees, and they are ubiquitous in applications. Recent work by the Galois project has provided a systematic approach for parallelizing irregular applications based on the idea of optimistic or speculative execution of programs. However, the overhead of optimistic parallel execution can be substantial. In this paper, we show that many irregular algorithms have structure that can be exploited and present three key optimizations that take advantage of algorithmic structure to reduce speculative overheads. We describe the implementation of these optimizations in the Galois system and present experimental results to demonstrate their benefits. To the best of our knowledge, this is the first system to exploit algorithmic structure to optimize the execution of irregular programs.

Adaptive execution techniques of parallel programs for multiprocessors

In simultaneous multithreading (SMT) multiprocessors, using all the available threads (logical processors) to run a parallel loop is not always beneficial due to the interference between threads and parallel execution overhead. To maximize the performance of a parallel loop on an SMT multiprocessor, it is important to find an appropriate number of threads for executing the parallel loop. This article presents adaptive execution techniques that find a proper execution mode for each parallel loop in a conventional loop-level parallel program on SMT multiprocessors. A compiler preprocessor generates code that, based on dynamic feedbacks, automatically determines at run time the optimal number of threads for each parallel loop in the parallel application. We evaluate our technique using a set of standard numerical applications and running them on a real SMT multiprocessor machine with 8 hardware contexts. Our approach is general enough to work well with other SMT multiprocessor or multicore systems.

Hardware Acceleration for Conditional State-Based Communication Scheduling on Real-Time Ethernet

Distributed real-time applications implement distributed applications with timeliness requirements. Such systems require a deterministic communication medium with bounded communication delays. Ethernet is a widely used commodity network with many appliances and network components and represents a natural fit for real-time application; unfortunately, standard Ethernet provides no bounded communication delays. Conditional state-based communication schedules provide expressive means for specifying and executing with choice points, while staying verifiable. Such schedules implement an arbitration scheme and provide the developer with means to fit the arbitration scheme to the application demands instead of requiring the developer to tweak the application to fit a predefined scheme. An evaluation of this approach as software prototypes showed that jitter and execution overhead may diminish the gains. This work successfully addresses this problem with a synthesized soft processor. We present results around the development of the soft processor, the design choices, and the measurements on throughput and robustness.

DynaQoS©‐RDF: a best effort for QoS‐assurance of dynamic reconfiguration of dataflow systems

AbstractThe significance of QoS‐assurance is being increasingly recognized by both the research and wider communities. In the latter case, this recognition is driven by the increasing adoption by business of 24/7 software systems and the QoS decline that end‐users experience when these systems undergo dynamic reconfiguration. At the beginning of 2006, the author set up a project named DynaQoS©‐RDF (QoS‐assurance of Dynamic Reconfiguration on Reconfigurable Dataflow Model), which was then sponsored by the CQ University Australia. Over the last two years, the author has investigated QoS‐assurance for dataflow systems, which are characterized by the pipe‐and‐filter architecture. The research has addressed issues such as: the global consistency of protocol transactions, the necessary and sufficient conditions for QoS‐assurance, execution overhead control for reconfiguration, state transfer for stateful components, and the design of a QoS benchmark. This paper discusses these research issues. It also proposes various QoS strategies and presents a benchmark for evaluating QoS‐assurance strategies for the dynamic reconfiguration of dataflow systems. This benchmark is implemented using the DynaQoS©‐RDF v1.0 software platform. Various strategies, including those from the research literature are benchmarked, and the best efforts for QoS‐assurance are identified. Copyright © 2008 John Wiley & Sons, Ltd.

Automatic Processor Customization for Zero-Overhead Online Software Verification

The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the program. The assertions validate the correctness of the software program without altering the program's temporal behavior in any way, a result never previously achieved by any online model-checking system. Additionally, the techniques and implementations described apply to any general purpose program and the absence of execution overhead renders the system ideal for the verification and debugging of real-time systems. Assertions are expressed in a simple subset of the property specification language (PSL), an IEEE standard originally intended for the behavioral specification of hardware designs. The target execution system is the eMIPS processor, a dynamically self-extensible processor realized with a field-programmable gate array (FPGA). The system can concurrently execute and check multiple programs at a time. Assertions are compiled into eMIPS Extensions, which are loaded by the operating system software into a portion of the FPGA, and discarded once the program terminates. If an assertion is violated, the program receives an exception, otherwise, it executes fully unaware of its verifier. The software program is not modified in any way. It can be compiled separately with full optimizations and executes with or without the corresponding hardware checker. The P2V compiler, implemented in Python, generates code for the implementation of the eMIPS processor running on the Xilinx ML401 development board. It is currently used to verify software properties in areas such as testing, debugging, intrusion detection, and the behavioral verification of concurrent and real-time programs.

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over $$\mathbb{F}_{{2^{{163}} }} $$ using Gaussian Normal Bases

This paper presents a comprehensive analysis of the design of custom instructions in a reconfigurable hardware platform dedicated to accelerate arithmetic operations in the binary field $$\mathbb{F}_{{2^{{163}} }} $$ , using a Gaussian normal basis representation. The resulting platform is capable of running real applications, thus allowing a precise measurement of the execution overheads, and a fair comparison of the hardware and software speedups at several implementation levels. By using this approach, we determine which field operations (e.g., multiplication) are better suited to constrained environments, and which ones provide an enhanced performance in general-purpose systems. Experimental results reveal that by using our fastest field multiplier implemented as a custom instruction in a combined hardware/software approach, we accelerate point multiplication (the fundamental operation in Elliptic Curve Cryptography) over 126 times.

Sweeper

The vulnerabilities that plague computers cause endless grief to users. Slammer compromised millions of hosts in minutes; a hit-list worm would take under a second. Recently proposed techniques respond better than manual approaches, but require expensive instrumentation, which limits deployment. Although spreading "antibodies" (e.g. signatures) ameliorates this limitation, hosts depending on antibodies are defenseless until inoculation; to the fastest hit-list worms this delay is crucial. Additionally, most recently proposed techniques cannot provide recovery to provide continuous service after an attack. We propose a novel solution called Sweeper that provides both fast and accurate post-attack analysis and efficient recovery with low normal execution overhead . Sweeper in-novatively combines several techniques: (1) Sweeper uses lightweight monitoring techniques to detect a wide array of suspicious requests, providing a first level of defense. (2) By cleverly leveraging lightweight checkpointing, Sweeper postpones heavyweight monitoring until absolutely necessary --- after an attack is detected. Sweeper rolls back and re-executes multiple times to dynamically apply heavyweight analysis techniques via dynamic binary instrumentation. Since only the execution involved in the attack is analyzed, the analysis is efficient, yet thorough. (3) Based on the analysis results, Sweeper automatically generates low-overhead antibodies to prevent future attacks of the same vulnerability. (4) Finally, Sweeper again re-executes to perform fast recovery for continuous service. We implement Sweeper in a real system. Our experimental results with three real-world servers and four real security vulnerabilities show that Sweeper can detect an attack and generate antibodies in under 60 milliseconds. Our results also show that Sweeper imposes under 1% overhead during normal execution, clearly suitable for widespread production deployment (especially since Sweeper also allows partial deployment). Finally, we analytically show that, for a fast hit-list worm otherwise capable of infecting all vulnerable hosts in under a second, Sweeper contains the extent of infection to under 5%.

Practical taint-based protection using demand emulation

Many software attacks are based on injecting malicious code into a target host. This paper demonstrates the use of a well-known technique, data tainting, to track data received from the network as it propagates through a system and to prevent its execution. Unlike past approaches to taint tracking, which track tainted data by running the system completely in an emulator or simulator, resulting in considerable execution overhead, our work demonstrates the ability to dynamically switch a running system between virtualized and emulated execution. Using this technique, we are able to explore hardware support for taint-based protection that is deployable in real-world situations, as emulation is only used when tainted data is being processed by the CPU. By modifying the CPU, memory, and I/O devices to support taint tracking and protection, we guarantee that data received from the network may not be executed, even if it is written to, and later read from disk. We demonstrate near native speeds for workloads where little taint data is present.

An Empirical Study of the Code Pitching Mechanism in the .NET Framework.

The .NET Compact Framework is designed to be a high-performance virtual machine for mobile and embedded devices that operate on Windows CE (version 4.1 and later). It achieves fast execution time by compiling methods dynamically instead of using interpretation. Once compiled, these methods are stored in a portion of the heap called the code cache and can be quickly reused to satisfy future method calls. While the code cache provides a high-level of reusability, it can also use a large amount of memory. As a result, the Compact Framework provides a “code pitching” mechanism that can be used to discard the previously compiled methods as needed. In this paper, we study the effect of code pitching on the overall performance and memory utilization of .NET applications. We conduct our experiments using Microsoft’s Shared-Source Common Language Infrastructure (SSCLI). We profile the access behavior of the compiled methods. We also experiment with various code cache configurations to perform pitching. We find that programs can operate efficiently with a small code cache without incurring substantial recompilation and execution overheads.