Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture

Abstract

This paper presents a mapping scheme of an optimized octree-based ray tracing algorithm and its implementation on a SIMD reconfigurable architecture, MorphoSys, with appropriate hardware incorporated. A two-level SIMD mapping scheme for ray tracing is chosen to get better trade-off between coherence exploitation efficiency and bandwidth requirements. We apply a SIMD octree traversal algorithm that supports ray traversals of any origins and directions. Moreover, we have applied the bottom-up traversal order for shadow and reflection rays to avoid unnecessary testing. The memory overhead of the parallel execution of ray tracing in SIMD systems is analyzed to direct memory optimization. Pre-fetching is utilized to hide data fetch latency behind the computation. A Spatial Partitioning Tree buffer reduces the latency due to the interleaved accesses to the shared memory. It also dynamically exploits ray coherence to save memory bandwidth. A Pointer Update Unit and a Pointer Buffer are combined to remove the overhead resulted from pointer-calculations and stack pushes during the parallel depth-first-traversal process. The associated hardware cost is less than 2% of the whole system. In order to include diffuse effects into the output, we apply spherical harmonic. Post-synthesis simulation shows that the target chip is estimated to be 33 mm 2 and consumes less than 1 W in the worst case. Cycle-accurate simulation demonstrates that interactive ray tracing for medium-sized scenes is achieved on MorphoSys.