Excimer Laser Annealing Research Articles

Laser induced ultrafast combustion synthesis of solution-based AlOx for thin film transistors

Excimer laser annealing (ELA) combined with combustion synthesis leads to high quality metal oxide TFTs in a short processing time.

Rapid photo-assisted activation and enhancement of solution-processed InZnO thin-film transistors

We demonstrate the rapid (<100 ns) activation and enhancement of solution-processed InZnO thin-film transistors (TFT) via a photo-assisted process: excimer laser annealing (ELA). A single shot is sufficient to enhance mobility from 0.19 cm2 V−1 s−1 to 3.91 cm2 V−1 s−1. Through multiphysics simulation, we confirmed that the process is instantaneous (<100 ns) and induces low substrate temperature suitable for flexible substrates. Analysis of optical properties, elemental concentration, and bonding changes after ELA revealed an improved metal-oxide formation and effective reduction of precursor-related impurities and oxygen vacancy traps. These demonstrate ELA’s potential for high-throughput fabrication of solution-processed devices for large-area, transparent, and flexible electronics.

62‐4: Late‐News Paper: Evaluation of polycrystalline silicon after Excimer laser annealing by Retardation measurement method

The excimer laser annealing (ELA) process is one of the important processes in Low Temperature Polycrystalline Silicon (LTPS) and the optimization of laser intensity and scan pitch in ELA process are the key technology to make good performance in OLED panel. However, the visual inspection through human eye has been used to find the Optimum ELA energy density (OPED) because of the fast inspection speed and accuracy. As the size of glass in LTPS is increasing, the need of a new inspection method has been raised. So the measurement of retardation which has been used in liquid crystals’ cell gap measuring was applied to evaluate the degree of crystallization in polycrystalline silicon(p‐Si) made from the ELA process for the first time. The origin of the retardation is estimated as a Laser‐induced periodic surface structure (LIPSS).

Sequential lateral crystallization of amorphous silicon on glass by blue laser annealing for high mobility thin-film transistors

We report the thickness effect of amorphous silicon for the polycrystalline silicon (poly-Si) layer laterally crystallized by blue laser annealing (BLA) using 50 μs melting time. The grain size is much larger and full width at half-maximum of Raman intensity is lower compared to those of the poly-Si by excimer laser annealing. It is found that the average width of lateral grain is wider than 3 μm and full width of half maximum of Raman intensity for the BLA poly-Si with an optimum thickness of 90 nm is 3.32 cm−1. The p-type poly-Si thin-film transistor with 90 nm exhibits field-effect mobility of 161.91 ± 6.14 cm2/Vs and subthreshold swing of 227 ± 7 mV/dec.

Improved performance of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge Ohmic contact andGe n&lt;sup&gt;+&lt;/sup&gt;/p diode by two-step annealing method

Silicon based germanium devices are crucial parts of optoelectronic integration as CMOS feature size continuously decreases. Germanium has attracted increasing attention due to its higher electron and hole mobility, larger optical absorption coefficient as well as lower processing temperature than those of silicon. However, the high diffusion coefficient and low solid solubility about n-type dopant and relatively high thermal budget required for high n-type doping in Ge make it difficult to achieve high activation n-type doping and excellent n&lt;sup&gt;+&lt;/sup&gt;/p shallow junction for source/drain in the nano-scaled n-MOSFET (here MOSFET stands for). The high activation concentration and shallow junction n-type doping in Ge are greatly beneficial to the scaled Ge n-MOSFET technology. In this work, the ohmic contact of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge and Ge n&lt;sup&gt;+&lt;/sup&gt;/p junction fabricated by a combination of low temperature pre-annealing process and excimer laser annealing for phosphorus-implanted germanium are demonstrated. Prior to excimer laser annealing, the samplesare annealed at a relatively low temperature, which can heal the implantation damages preliminarily. Through the optimization of pre-annealing temperature and time, the low temperature pre-annealing step can play a critical role in annihilating the implantation damages and significantly suppressing phosphorus diffusion in the laser annealing process, resulting in a very small dopant diffusion length at a high activation level of phosphorus. Through the combination of ion implantation and two-step annealing technology, the specific contact resistivity (&lt;i&gt;ρ&lt;/i&gt;&lt;sub&gt;C&lt;/sub&gt;) of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge Ohmic contact is measured by CTLM structure. The optimized annealing condition is 400 &lt;sup&gt;o&lt;/sup&gt;C-10 min of low temperature annealing and 150 mJ/cm&lt;sup&gt;2&lt;/sup&gt; of ELA. Under that annealing condition, the ρ&lt;sub&gt;C&lt;/sub&gt; of the sample by two-step annealing is reduced to 2.61 × 10&lt;sup&gt;–6&lt;/sup&gt; Ω·cm&lt;sup&gt;2&lt;/sup&gt;, which is one order of magnitude lower than that by ELA alone (about 3.44 × 10&lt;sup&gt;–4&lt;/sup&gt; Ω·cm&lt;sup&gt;2&lt;/sup&gt;). The lower value of &lt;i&gt;ρ&lt;/i&gt;&lt;sub&gt;C&lt;/sub&gt; for the sample with LTPA can contribute to the higher carrier concentration and better crystalline quality thanthat without LTPA, which is confirmed by SRP and TEM. Moreover, the rectification ratio of Ge n&lt;sup&gt;+&lt;/sup&gt;/p junction diode is improved to 8.35 × 10&lt;sup&gt;6&lt;/sup&gt; at ± 1 V, which is two orders of magnitudes higher than that by ELA alone. And a lower ideality factor of about 1.07 is also obtained than that by ELA alone, which indicates that the implantation damages can be repaired perfectly by two-step annealing method.

Review—Technology Trends of Poly-Si TFTs from the Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing low-temperature polycrystalline-Si (LTPS) are critical for system-on-panel applications. The requirements for LTPS are a high quality, a large grain size and position control of the nucleation. Many promising crystallization methods have been developed to satisfy these requirements. Herein, two scientific discoveries related to the low-temperature crystallization and high-performance TFT structure using the tunnel effect are introduced. Hydrogens in an amorphous (a-Si) film greatly accelerate the crystal velocity and improved the crystallinity of the excimer-laser annealing (ELA) poly-Si film, thereby providing a high-quality, a large-grained film referred to as secondary-grain film, under the solid-phase condition. In addition, a soft X-ray crystallization (SXC) method was developed. It reduces the threshold temperature of crystallization for a-Si, SiXGe1-X and Ge films by 100°C–140°C in comparison to that for films prepared by conventional thermal crystallization. The SXC method is expected to become the critical low-temperature crystallization method in the era of the flexible electronics. On the other hand, although high-performance TFTs that utilize large single-crystalline grains have been intensively researched, such research has not been successful from the viewpoint of mass production. A novel device structure – tunneling dielectric TFT (TDTFT)–has been developed. The TDTFT reduces the gate-off current to less than 1/10 of that with a conventional TFT. In addition, the TDTFT improved the hump effect. We conclude that the triple-gate (Fin) TDTFT will be a promising candidate for next-generation poly-Si TFT structures.

Chemical and structural analysis of low-temperature excimer-laser annealing in indium-tin oxide sol-gel films

We investigated the influence of excimer-laser annealing (ELA) on the electrical, chemical, and structural properties of indium–tin oxide (ITO) films prepared by a solution process. The ITO film was prepared by the sol-gel method and annealed by excimer-laser pulses with an energy density up to 240 mJ/cm2. Hall measurements showed that the ELA substantially enhanced the electrical properties of the ITO films, including their resistivity, carrier density, and mobility, as increasing the laser energy density. In-depth x-ray photoelectron spectroscopy analysis of the chemical states in the film surface showed that the ELA reduced carbon species and promoted both an oxidation and crystallization. These changes were consistent with results of x-ray diffraction and transmission electron microscopy measurements, where expansions in the microcrystal growth were observed for higher laser energy density. We comprehensively understand that the chemical rearrangement and concomitant crystallization are the main factors for achieving the electrical properties during the ELA. These results suggest the potential of the ELA-treated sol-gel films for providing high-quality ITO films at low temperatures toward the flexible device applications.

Synthesis and Formation Mechanism of All-Organic Block Copolymer-Directed Templating of Laser-Induced Crystalline Silicon Nanostructures.

This report describes the generation of three-dimensional (3D) crystalline silicon continuous network nanostructures by coupling all-organic block copolymer self-assembly-directed resin templates with low-temperature silicon chemical vapor deposition and pulsed excimer laser annealing. Organic 3D mesoporous continuous-network resin templates were synthesized from the all-organic self-assembly of an ABC triblock terpolymer and resorcinol-formaldehyde resols. Nanosecond pulsed excimer laser irradiation induced the transient melt transformation of amorphous silicon precursors backfilled in the organic template into complementary 3D mesoporous crystalline silicon nanostructures with high pattern fidelity. Mechanistic studies on laser-induced crystalline silicon nanostructure formation revealed that the resin template was carbonized during transient laser-induced heating on the milli- to nanosecond timescales, thereby imparting enhanced thermal and structural stability to support the silicon melt-crystallization process at temperatures above 1250 °C. Photoablation of the resin material under pulsed excimer laser irradiation was mitigated by depositing an amorphous silicon overlayer on the resin template. This approach represents a potential pathway from organic block copolymer self-assembly to alternative functional hard materials with well-ordered 3D morphologies for potential hybrid photovoltaics, photonic, and energy storage applications.

Electrical evaluation of the crystallization characteristics of excimer laser annealed polycrystalline silicon active layer

We showed that the crystallinity of polycrystalline silicon (poly-Si) active layer of low temperature poly silicon (LTPS) devices can be comparatively analyzed through conventional electrical methods. We fabricated the MOS capcitors and the thin film transistors (TFT) with different excimer laser annealing (ELA) crystallization conditions. Through the capcitance–time (C–t) method and the frequency variable capacitance–votage (C–V) method, we detected the influence of grain boundaries of poly-Si. The generation lifetime (τg) and the number of border traps (Nbt) calculated by these methods could detect tiny crystallinity differences related to energy density differences about 10–15 mJ/cm2 during the recrystallization. The field effect mobility (μFE) and off current (Ioff) measured with the TFTs also showed the same tendency. The results of this study show that the measurements using MOS capacitor are sufficiently reliable and suitable for obseving property changes of the poly-Si active layer.

LTPS Thin-Film Transistors Fabricated Using New Selective Laser Annealing System

Selective laser annealing system was developed to realize fabrications of low-temperature poly-Si thin-film transistors (TFTs) even for large substrate, while the conventional excimer laser annealing system has the limitation in substrate size due to the difficulty in obtaining uniform beam line. In this paper, this new system was applied to fabricate poly-Si TFTs, using two laser exposure methods such as the static exposure and the scan exposure. Grain size increased as the laser energy density increased, and TFTs with the field-effect mobility larger than 100 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> with the ON- OFF ratio of drain current of approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> could be obtained. Furthermore, for the scan exposure, periodic grain structure was observed resulting from the lateral solidification. In this condition, variations of electrical properties of TFT could be reduced compared to the case of the static exposure.

Effects of excimer laser annealing energy on the properties of thermally evaporated tin antimony sulfide thin films and TEM characterization of the powder

Tin antimony sulfide (TAS) is one of the most promising compounds for the next generation of optoelectronic and thin film photovoltaic devices. TAS material was synthesized by a solid-state reaction using earth-abundant tin, antimony and sulfur elements. The structural properties of the TAS powder were investigated by transmission electron microscopy (TEM). X-ray diffraction (XRD), high-resolution transmission electron microscopy (HRTEM) and selected electron diffraction (SAED) were employed to establish the crystalline nature of the powder. The TEM observations demonstrated that the powder was polycrystalline in nature with rod-shaped structure. The effects of excimer laser annealing (ELA) at different pulse energies on the structural, morphological and optical properties of thermally evaporated TAS films were investigated. X-ray diffraction (XRD), scanning electron microscopy (SEM) and Raman spectroscopy measurements showed that the films annealed by an excimer laser of 248 nm were amorphous for weak energy densities whereas the sample irradiated with 111 mJ/cm− 2 was polycrystalline with a preferential $${\text{(}}\overline {{\text{2}}} {\text{1}}\overline {{\text{3}}} {\text{)}}$$ orientation. The ELA effects on the optical properties were also studied in the wavelength range 300–1800 nm by using UV–Vis–NIR spectroscopy. The absorption coefficient of all samples in the fundamental absorption region is higher than 104 cm−1. We also found that the optical band gap decreases from 2.04 to 1.84 eV after irradiating the thin films under different laser energy densities.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

(Invited) Advanced Crystallization Using Blue Laser-Diode Annealing for Low Temperature Poly Si TFTs

Laser Crystallizations using Blue Laser-Diodes Annealing (BLDA) as well as conventional Excimer Laser Annealing (ELA) are discussed for mounting the TFTs on flexible panels. On glass, high crystallinity of Si films can be obtained by using multi-shots ELA as well as CW laser scanning [1, 2]. There are some issues for Si film after ELA, such as rough Si surface or shots MURA including the fabrication cost. As a result of scanning BLDA for thin Si films, remarkable crystallization occurs with keeping the surface smooth not only for CVD film but also for sputtered Si film [3]. By changing the laser power of 445 nm beam, the grain size can be controlled from micro-grains to large grains as well as to anisotropic long crystal grains [4]. For the Si films of heavily phosphorus doped condition, the resistivity decreased drastically due to the increase in the carrier mobility with high carrier concentration after BLDA of single beam scanning as well as after multi-shots ELA [5]. To realize high performance poly Si films directly not only on flexible glass [6] but also on flexible plastic sheet, effective laser annealing for high quality Si film by low temperature deposition is expected and a design for the thermal buffer layers on flexible sheet is effective [7]. To perform ultra-low temperature TFT process, metal source/drain structure without using ion implantation is also proposed. High performance poly Si TFTs with low fabrication cost on flexible panel should be possible not only for n-channel but also for p-channel [8, 9]. References M. Tai, M. Hatano, S. Yamaguchi, S. K. Park, T. Noda, M. Hongo, T. Shiba and M. Ohkura, Proc. of AM-LCD, TFT3-3, p.231 (2002)T. Noguchi, Mat. Res. Soc. Symp. Proc., 557, p.213 (1993),T. Okada, K, Sugihara, S. Chinen and T. Noguchi, J. Korean Phys. Soc., 66, No.8, pp.1266-1269 (2015). .T. Noguchi, J. Inf. Display, 11, No.1, p.12 (2010).T. Noguchi and T. Okada, J. of Inf. Display, 15, No.1, p.47 (2014).T. Harada, F. Gakiya, Y. Ishiki, T. Okada, T. Noguchi, K. Noda, A. Suwa and H. Ikenoue, Proc. of IDW, AMDp2-11L, p.444 (2016).T. Okada, J.D. Mugiraneza, K. Shirai, T. Suzuki, T. Noguchi, H. Matsushima, T. Hashimoto, Y. Ogino and E. Sahota, Jap. J. Appl. Phys. 51, 03CA02 (2012).K. Sugihara, K. Shimoda, T. Okada and T. Noguchi, J. Inf. Display, 18, No.4, 173-176 (2017).T. Ashitomi, T. Harada, T. Okada, T. Noguchi, O. Nishikata and A. Ota, J. Inf. Display, 18, No.4, 185-189 (2017).

Integration Challenges of Flash Lamp Annealed LTPS for High Performance CMOS TFTs

The development of low-temperature polycrystalline silicon (LTPS) based on excimer laser annealing (ELA) has realized CMOS TFTs with notable electrical performance. The flat-panel display industry is searching for alternative LTPS strategies which are cost-effective and easily scalable to large glass panel production, which has led to recent interest in the application of flash-lamp annealing (FLA) for the LTPS crystallization process. The FLA-LTPS process exposes large areas of amorphous silicon with high irradiance from xenon flashlamps for pulse durations that are in microsecond timescale. Amorphous silicon absorbs a sufficient portion of the xenon emission spectrum to melt and crystallize into polysilicon while staying within the thermal constraints of the underlying glass substrate. Multi-lamp exposure systems with high repetition pulse rates would potentially offer significant advantages in manufacturing throughput and cost. The application of FLA-LTPS for CMOS TFTs has been recently reported, with best-case performance comparable to ELA-LTPS. Investigations to improve upon this technology are in progress to address integration challenges to reduce variation in device operation and enable device scaling. The focus areas of this work are material uniformity, source/drain dopant activation, and defect passivation; all of which are fundamental issues facing FLA-LTPS TFTs. The importance of patterning the amorphous silicon film into separate super-mesa elements prior to FLA crystallization was previously established. The FLA system for this work was a NovaCentrix PulseForge 3300 system, used to crystallize polygons of a-Si with a 100 nm SiO2 capping layer. The FLA response of densely packed mesa arrays exhibits a proximity effect which impedes the melting of interior mesas, whereas exterior mesas demonstrate a crystallization response consistent with isolated mesas. This comparison is highlighted in Fig. 1 by the pronounced gradient in crystallization morphology. These observations have led to a theory of competing rates between solid-phase and liquid-phase crystallization, hypothesized due to the large difference between the melting points of amorphous and crystalline silicon. The challenge of dopant activation is exacerbated by the need to limit lateral diffusion. Dopants within silicon that has entered a liquid phase will experience dramatically enhanced diffusion, even within the ultra-short pulse duration of the FLA process. The result is a compromised intrinsic channel which limits device scaling. Thus, dopants must be introduced into post-FLA LTPS and activated at glass-compatible temperatures, which is also a requirement for self-aligned devices. Solid-phase dopant activation in FLA-LTPS films has been investigated using furnace annealing and multiple shot FLA exposures at lower intensity. Pre-amorphizing the source/drain regions with electrically inactive species has also been explored. Hydrogen passivation treatments using both plasma and sintering processes have been investigated in efforts to reduce the influence of defect states. Pre-amorphization and passivation processes have yielded promising device characteristics with low series resistance, low leakage current, and high carrier mobility, as shown in Fig. 2. Figure 1

Fast Fabrication of SOFCs with Screen-Printed YSZ Electrolyte Films By Flash Light Sintering

Solid oxide fuel cells (SOFCs) are attractive energy conversion system because of their high energy conversion efficiency, fuel flexibility and no emission of pollutant. SOFCs are composed of a dense electrolyte and two porous electrodes of anode and cathode. In the fabrication of SOFCs, many fabrication techniques such as screen-printing, tape casting, sol-gel, sputtering, chemical vapor deposition (CVD) and atomic layer deposition (ALD) are used to fabricate the solid electrolyte and the electrodes. Among various fabrication techniques, screen-printing is most widely used method in the industry because it is easy, scalable and economical process. Meanwhile, for the fabrication of solid electrolyte in this technique, high temperature sintering process is essential because the electrolyte should be fully densified to prevent any penetration of electrons and fuels. However, this high process temperature takes a considerable amount of time and thus causes significant manufacturing costs. Therefore, reducing the sintering temperature and long process time is one of the major challenges to reduce the fabrication cost and facilitate the commercialization of SOFCs. In recent years, to address these issues, many researchers demonstrated alternative sintering processes to reduce the sintering temperature and process time. For example, several researchers proposed rapid thermal annealing (RTA) process as an alternative sintering process because it can raise temperature to the target temperature within short time [1,2]. However, this process still requires relatively long maintaining and cooling processes. In addition, the excimer laser ablation annealing and the microwave sintering process have been also suggested but there are still limitations such as extremely narrow spot size and complexity of microwave interactions with materials respectively [3,4]. On the other hand, the flash light sintering process presented here uses white light flash irradiation with a broad visible wavelength range as a heat treatment source and this process has many advantages such as simplicity, scalability, and cost-effectiveness. Above all, because this process conducted within a few seconds at room temperature under ambient conditions, it can effectively reduce the manufacturing time and cost. Our previous works successfully demonstrated that the YSZ thin films deposited by solution-based process was annealed by flash light sintering and it showed comparable material properties to the conventional thermal sintering process [5]. In this work, the YSZ electrolyte films were fabricated by conventional screen-printing method and flash light sintering process was employed as an alternative sintering process of conventional thermal sintering method. In the sintering process, the effect of various pulse conditions and additional substrate heating were investigated. Microstructure, crystallinity and sintering behaviors of sintered films were analyzed to demonstrate the effectiveness of flash light sintering process. Reference [1] Wang, S. J. & Ong, C. K. Rapid thermal annealing efect on crystalline yttria-stabilized zirconia gate dielectrics. Semiconductor Science and Technology 18, 154 (2003). [2] Beltrán, N. H., Balocchi, C., Errazu, X., Avila, R. E. & Piderit, G. Rapid thermal annealing of zirconia flms deposited by spray pyrolysis. Journal of Electronic Materials 27, L9–L11 (1998). [3] Hao, H., Xu, L., Huang, Y., Zhang, X. & Xie, Z. Kinetics mechanism of microwave sintering in ceramic materials. Science in China Series E: Technological Sciences 52, 2727–2731 (2009). [4] Bayati, R. et al. Modifcation of properties of yttria stabilized zirconia epitaxial thin flms by excimer laser annealing. ACS applied materials & interfaces 6, 22316–22325 (2014). [5] Park, J.S. et al. Rapid, cool sintering of wet processed yttria-stabilized zirconia ceramic electrolyte thin films. Scientific reports 7, 12458 (2017)

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal layer was adopted to suppress leakage current caused by light coming from backlight system. Different off-current behavior as each other electrical connection of metal layer was observed, source-contacted or floating bottom metal showed the high leakage current by increasing current flow through back-channel at off states while gate-contacted bottom metal have comparable low leakage current with non-bottom metal layer. This leakage current characteristic was verified by technology computer-aided design (TCAD) simulation. Objectives and Background A low temperature polycrystalline silicon (LTPS) have been widely used for in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode displays (AMOLEDs) as thin film transistor (TFT) backplane and system on panel (SOP), combined with controller, memory, and driver circuits, due to excellent electrical characteristics. The LTPS TFT based displays can achieve high brightness, high aperture ratio, high resolution, and low power consumption due to excellent electrical characteristics. On the other hand, in display product with high luminance backlight system, such as auto and mobile products, the LTPS TFTs require a bottom metal layer to reduce leakage current caused by light coming from backlight unit (BLU). This bottom metal layer in contacted with gate or source electrodes is applied under the poly-Si layer. However, this bottom metal layer may also affect seriously the leakage current of diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in SOP. In this study, the leakage current of LTPS diode for ESD protection was investigated with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. We measured the electrical characteristics with variation of electrical connection of bottom metal layer. Also, the technology computer-aided design (TCAD) simulation was performed to analyze the physical mechanism. From analysis results, optimized bottom metal design of LTPS diode was proposed for ESD production. Experiment Figure 1 shows the top-gate coplanar n-channel LTPS TFT structure with bottom metal layer under poly-Si. Gate and Drain electrodes were connected to common electrode in LTPS TFTs structure for LTPS diode. This LTPS diode was fabricated at low temperature of less than 450°C on glass substrate. The standard commercial NMOS processes, including the ion implantation, the excimer laser annealing (ELA), and the rapid thermal annealing (RTA), were employed in this experiment. To observe the electrical characteristics of LTPS diode, I-V characteristics were measured by using an Agilent B1500A semiconductor analyzer at room temperature. Results and Discussion Figure 2 shows I-V characteristics of LTPS diodes with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. The leakage current with source-contacted and floating bottom metal increased considerably compared with non-bottom metal. Especially, the leakage current with source-contacted bottom metal increased more than with floating bottom metal. On the other hand, the leakage current with gate-contacted bottom metal was low enough to be comparable with non-bottom metal. To analyze this phenomenon, we observed the electron concentration distribution within poly-Si at VGS= 0V, 10V, and -10V region using technology computer-aided design (TCAD) simulation as shown figure 3. For source-contacted bottom metal and floating bottom metal, at VGS= -10V, the electron was accumulated in the back-channel of poly-Si since the positive voltage is applied to back-channel by voltage difference between drain and bottom metal even though drain (=gate) electrode is applied to negative voltage. Therefore, at VGS= -10V, the leakage current flows through the back-channel in LTPS diodes with source-contacted bottom metal and floating bottom metal. But, for LTPS diode with gate-contacted bottom metal, when drain electrode was applied to negative voltage, there is no different voltage bottom metal and gate electrode because these electrodes were linked in common. Therefore, LTPS diode with gate-contacted bottom metal has low leakage current as comparable with non-bottom metal. Conclusion In summary, the leakage current of LTPS diode was strongly dependent on electrical connection of bottom metal layer. The electrical connection of bottom metal affects back-channel region within poly-Si due to the difference between bottom metal and drain electrodes at off region. Especially, LTPS diode with source-contacted bottom metal and floating bottom metal increased considerably the leakage current, while, gate-contacted bottom metal decreased leakage current. Therefore, bottom metal layer should be connected by gate electrode in LTPS diode for ESD protection. Figure 1

Integration Challenges of Flash Lamp Annealed LTPS for High Performance CMOS TFTs

This work demonstrates a method of producing polycrystalline silicon TFTs using Flash Lamp Annealing (FLA) as a potential industrial counterpart to excimer laser annealing. Material uniformity and low-temperature dopant activation are explored within an investigation on solid-phase epitaxial regrowth for PMOS TFTs. Silicon self-implantation is used to partially amorphize select regions of FLA LTPS material, allowing epitaxial regrowth to incorporate boron into the resulting lattice. This regime is compared with total amorphization, in which epitaxial regrowth cannot occur. The effects of these different methods of recrystallization are demonstrated through transfer characteristics of fabricated transistors. Devices utilizing a partial pre-amorphization of FLA LTPS demonstrated effective hole channel mobilities of 40 - 50 cm2/(Vs) in low drain bias operation. Additionally, self-aligned TFTs using FLA are presented for the first time, with effective hole channel mobilities of 30 - 60 cm2/(Vs) in low drain bias operation using the same treatment.

Thermal recrystallization of short-range ordered WS2 films

The integration of van der Waals materials in nanoelectronic devices requires the deposition of few-layered MX2 films with excellent quality crystals covering a large area. In recent years, astonishing progress in the monolayer growth of WS2 and MoS2 was demonstrated, but multilayer growth resulted often in separated triangular or hexagonal islands. These polycrystalline films cannot fully employ the specific MX2 properties since they are not connected in-plane to the other domains. To coalesce separated islands, ultrahigh-temperature postdeposition anneals in H2S are applied, which are not compatible with bare silicon substrates. Starting from the deposition of stoichiometric short-ordered films, the present work studies different options for subsequent high-temperature annealing in an inert atmosphere to form crystalline films with large grains from stoichiometric films with small grains. The rapid thermal annealing, performed over a few seconds, is compared to excimer laser annealing in the nanosecond range, which are both able to crystallize the thin WS2. The WS2 recrystallization temperature can be lowered using metallic crystallization promoters (Co and Ni). The best result is obtained using a Co cap, due to the circumvention of Co and S binary phase formation below the eutectic temperature. The recrystallization above a critical temperature is accompanied by sulfur loss and 3D regrowth. These undesired effects can be suppressed by the application of a dielectric capping layer prior to annealing. A SiO2 cap can suppress the sulfur loss successfully during annealing and reveals improved material quality in comparison to noncapped films.

57‐5: Invited Paper: Excimer Laser Annealing and Spot‐Beam Crystallization of Si Films for Advanced Displays

This paper discusses recent laser‐crystallization‐related research results and advances that are enabling us to: (1) gain an in‐depth understanding of the ELA method currently utilized in the industry, and (2) suggest that a quasi‐CW fiber‐laser‐based SBC technique can be developed into a viable laser annealing method.

Using KrF ELA to Improve Gate-Stacked LaAlO₃/ZrO₂ Indium Gallium Zinc Oxide Thin-Film Transistors with Novel Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition Technique.

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique and KrF excimer laser annealing (ELA) were employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO-TFTs). Device with a 150 mJ/cm2 laser annealing densities demonstrated excellent electrical characteristics with improved on/off current ratio of 4.7×107, high channel mobility of 10 cm2/V-s, and low subthreshold swing of 0.15 V/dec. The improvements are attributed to the adjustment of oxygen vacancies in the IGZO channel to an appropriate range of around 28.3% and the reduction of traps at the high-k/IGZO interface.